Verilog-A models in IHP OpenPDK for a modern SiGe RF process
Speaker: Dietmar Warning email: warning@ihp-microelectronics.com
The presentation shows the application of Verilog-A models for the most important active and passive devices of IHP SiGe 130nm generation II process.
It will be demonstrated how the Compact Model Coalition (CMC) certified models compiled by OpenVAF and implemented into the PDK ngspice library. Pro's and Con's of this approach compared to built-in models of the simulator with the open source schematic capture tool Qucs-s are illustrated by means of realistic RF circuit design examples.
The abilities and missing capabilities of the actual available models for temperature, corner and mismatch evaluations are demonstrated and workarounds for missing features are presented.
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General information
- Source Verilog-A models for NGSPICE and XYCE: https://github.com/dwarning/VA-Models
- IHP OpenPDK SG13G2 process: https://github.com/IHP-GmbH/IHP-Open-PDK/tree/dev
- NGSPICE source and binary repository: https://sourceforge.net/projects/ngspice/