Update on the Efabless "Frigate" next-generation harness chip, the "Panamax" padframe design, and results from the "Chipalooza"
- Speaker(s): Tim Edwards
- email: tim@opencircuitdesign.com
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Abstract
This lightning talk gives an update on activities which were ongoing at Efabless at the time of the company shutdown, and how they are being carried forward in the public domain.
The "Frigate" chip was intended to be the next-generation "harness" chip after Caravel. Caravel was a popular platform for user designs, incorporating a padframe, RISC-V processor, and some peripheral communication subsystems like UART and SPI, and was used on hundreds of projects through more than a dozen shuttle runs. "Frigate" starts with a new padframe design called "Panamax" with 130 pins and GPIO arranged in nine banks of 8 bits each, which itself is the basis of a new "Panamax openframe" platform. "Frigate" adds a more capable Hazard-3 RISC-V processor and many more peripherals including UART, I2C, I2S, SPI, and USB. It has a programmable analog subsystem with DACs and ADCs, comparators, op-amps, instrumentation amplifiers, and sensors. The programmable analog block includes many circuits designed for the Efabless "Chipalooza" challenge, making the Frigate chip a community effort.
This talk covers the recent fork of these projects to the FOSSi Foundation, new development work, and test tapeouts on Sky130.
General information
- Repositories:
- https://github.com/fossi-foundation/frigate - https://github.com/fossi-foundation/frigate_analog - https://github.com/RTimothyEdwards/chipalooza_projects_2
- Documentation: See documentation included with each repository