Towards open-source functional verification methodologies
Abstract
Functional verification is a critical aspect of modern chip design, ensuring that complex digital ICs function as intended. While open-source projects such as Verilator, Cocotb, or ChiselVerify have focused on essential verification tools such as complex assertions, coverage, or constrained randomization, relatively little attention has been given to methodologies for building verification infrastructure at larger scales in the respective open-source frameworks. The Universal Verification Methodology (UVM) is an open industry standard methodology for building such a scalable verification infrastructure. However, currently, no open-source simulator supports all the necessary SystemVerilog features to use the UVM. While PyUVM provides an accessible alternative in Python, it remains a direct translation of the UVM, inheriting design choices tied to SystemVerilog’s language constraints.
This presentation will argue for leveraging modern general-purpose programming languages to build open-source verification environments that incorporate methodologies suited to the language's strengths. We propose a Scala-based verification framework built on the core principles of the UVM, which are simplified where possible to arrive at a minimal methodology for constructing composable and scalable testbenches. This approach showcases the potential of using modern languages for verification to improve productivity and close the gap to contemporary software development practices.
- Speaker(s): Tjark Petersen
- email: tjape@dtu.dk
- Repository: https://github.com/tjarker/framework