The potential for asynchronous circuits to bridge the hardware / software divide

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  • Speaker(s): Edward Bingham (Ned), Broccoli LLC
  • email: edward.bingham@broccolimicro.io

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Abstract

How much of your chip design is spent just wiring up bloated proprietary tools? Hardware should not require a thousand-person team.

Hardware and software are designed using fundamentally different paradigms. While software developers work with behavioral abstractions (describing what the system should do), hardware designers are forced to reason structurally (specifying how components are instantiated and interconnected). This structural approach is not how most people reason, creating a steep barrier for software developers entering hardware.

Today’s circuit design methodologies rely on tight timing and other physical assumptions, making it possible for high-level synthesis to fail. As a result, it is often challenging to generate a structural implementation that is functionally correct let alone performant, and hardware designers must continue to reason at the structural level to fill the gap.

This talk introduces Loom, an open-source toolchain that reimagines the EDA flow from the ground up. Loom synthesizes to Quasi-Delay Insensitive (QDI) asynchronous circuits, which make the fewest possible assumptions about the underlying physics. In principle, this enables a synthesis path from behavioral specifications to layout that is correct by construction.

Historically, there have been two key blockers: (1) the state encoding problem, where all reachable states must be uniquely encoded, and (2) arbitrarily complex stateholding elements, which are often required in QDI logic but do not map well to standard cell libraries. Loom is tackling these challenges directly, expanding on petri-net semantics with guarded commands, and providing a custom-cell layout engine targeting open PDKs. Although Loom's approach to state variable insertion is still under development, Loom represents a concrete step toward a more robust, accessible, and software-like experience for digital hardware design.

We’re unwinding 50 years of complexity. Today’s hardware has more room to breathe.

Software

General information

Roadmap

  • High level synthesis and FPGA agnostic backend by 2026
  • The project seeks help on: identifying which toolchains are seeing the most use/development/production locally, and potential integrations and long-term partnerships.

If you're working on another hardware language or compilation flow, I'd love to chat.

References