The Raven chip: First-time silicon success with qflow and efabless
- Speaker: Tim Edwards
- email: tim@efabless.com
- other information: http://efabless.com http://opencircuitdesign.com
Slides
Talk_title_name.pdf (to upload a file: go to Edit mode, then click on the fourth icon from the left "Embed file" and follow the instructions)
Abstract
The Raven chip is a proof-of-concept ASIC and reference design created on the efabless design platform using all open-source EDA tools. In addition to using open-source tools, the Raven chip itself is open source in hardware, software, and firmware. Open source layout is made possible by the use of tools such as qflow, magic, and netgen, and the use of abstracted views of core components. By presenting a viewable layout of the reference design and making available all the tools and documentation needed to create and validate it, the process of making a custom microprocessor can be accomplished by a single person in a matter of weeks. To complete the proof-of-concept, the Raven chip was manufactured on X-Fab XH018 and tested, and successfully operates at a core clock rate of 100MHz.
Software
General information
- Repository: http://efabless.com and https://github.com/efabless/picorv32-soc-raven
- Main documentation website: http://efabless.com (register and log in, find entry in the Marketplace catalog)
- Wikipedia page: https://en.wikipedia.org/wiki/magic_(software) (only known wikipedia article on the EDA tools)
- Wiki page on wiki.f-si.org: https://wiki.f-si.org/index.php/XXX-YYY-ZZZ
- The software has been used in the following projects: efabless Hydra, efabless Raven, projects by NASA Goddard, Ozark IC, MultiGiG, Asic Advantage, and others.
Roadmap
- The software wishes to interface with the following tools: abk-openroad, coriolis
- The project seeks help on: IR drop analysis, electromigration analysis, dynamic power estimation