Difference between revisions of "The Raven chip: First-time silicon success with qflow and efabless"

From F-Si wiki
Jump to navigation Jump to search
(Created page with "* Speaker(s): Xxx Yyy * email: xx@yy.zz (voluntary information -it will help others to contact you in case of need) * other information: xxx ==Slides== Media:Dummy slide.pd...")
 
 
(3 intermediate revisions by 2 users not shown)
Line 1: Line 1:
* Speaker(s): Xxx Yyy
* Speaker: Tim Edwards
* email: xx@yy.zz (voluntary information -it will help others to contact you in case of need)
* email: tim@efabless.com
* other information: xxx
* other information: http://efabless.com http://opencircuitdesign.com


==Slides==
==Downloads==
[[Media:Dummy slide.pdf|Talk_title_name.pdf]] (to upload a file: go to Edit mode, then click on the fourth icon from the left "Embed file" and follow the instructions)
* [[:File:Qflow Raven FSiC2019.pdf|Slides]]
* [https://peertube.f-si.org/videos/watch/e8404429-4d32-4741-ac11-1beb0f16348e Video recording]


==Abstract==
==Abstract==
Lorem Ipsum<ref>E. Miller, ''The history of Lorem Ipsum'', (New York: Academic Press, 2005), 23-5.</ref> is simply dummy text of the printing and typesetting industry. Lorem Ipsum has been the industry's standard dummy text ever since the 1500s, when an unknown printer took a galley of type and scrambled it to make a type specimen book. It has survived not only five centuries, but also the leap into electronic typesetting, remaining essentially unchanged. It was popularised in the 1960s with the release of Letraset sheets containing Lorem Ipsum passages, and more recently with desktop publishing software like Aldus PageMaker including versions of Lorem Ipsum.<ref>R. Smith, "Dummy text repositories", ''Scientific American'', 46 (April 1978): 44-6.</ref>
The Raven chip is a proof-of-concept ASIC and reference design created on the efabless design platform using all open-source EDA tools.  In addition to using open-source tools, the Raven chip itself is open source in hardware, software, and firmware. Open source layout is made possible by the use of tools such as qflow, magic, and netgen, and the use of abstracted views of core components. By presenting a viewable layout of the reference design and making available all the tools and documentation needed to create and validate it, the process of making a custom microprocessor can be accomplished by a single person in a matter of weeks. To complete the proof-of-concept, the Raven chip was manufactured on X-Fab XH018 and tested, and successfully operates at a core clock rate of 100MHz.


==Software==
==Software==
===General information===
===General information===
* Repository: https://xxxx.yyy
* Repository: http://efabless.com and https://github.com/efabless/picorv32-soc-raven
* Main documentation website: https://xxxx.yyy
* Main documentation website: http://efabless.com (register and log in, find entry in the Marketplace catalog)
* Wikipedia page: https://en.wikipedia.org/wiki/XXX-YYY-ZZZ (if a wikipedia page about the software, or a page mentioning it, does not exist yet, please consider creating one). If it gets reverted or deleted, please create a page on https://wiki.f-si.org
* Wikipedia page: https://en.wikipedia.org/wiki/magic_(software) (only known wikipedia article on the EDA tools)
* Wiki page on wiki.f-si.org: https://wiki.f-si.org/index.php/XXX-YYY-ZZZ
* The software has been used in the following projects: efabless Hydra, efabless Raven, projects by NASA Goddard, Ozark IC, MultiGiG, Asic Advantage, and others.
* The software has been used in the following projects: XXX, YYY, ZZZ


===Roadmap===
===Roadmap===
* The software wishes to interface with the following tools: XXX, YYY
* The software wishes to interface with the following tools: abk-openroad, coriolis
* The project seeks help on: XXX, YYY
* The project seeks help on: IR drop analysis, electromigration analysis, dynamic power estimation


==References==
==References==
<references />
<references />

Latest revision as of 00:06, 12 November 2019

Downloads

Abstract

The Raven chip is a proof-of-concept ASIC and reference design created on the efabless design platform using all open-source EDA tools. In addition to using open-source tools, the Raven chip itself is open source in hardware, software, and firmware. Open source layout is made possible by the use of tools such as qflow, magic, and netgen, and the use of abstracted views of core components. By presenting a viewable layout of the reference design and making available all the tools and documentation needed to create and validate it, the process of making a custom microprocessor can be accomplished by a single person in a matter of weeks. To complete the proof-of-concept, the Raven chip was manufactured on X-Fab XH018 and tested, and successfully operates at a core clock rate of 100MHz.

Software

General information

Roadmap

  • The software wishes to interface with the following tools: abk-openroad, coriolis
  • The project seeks help on: IR drop analysis, electromigration analysis, dynamic power estimation

References