Difference between revisions of "SystemC AMS and upcoming free frameworks for the free design"

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This talk will introduce SystemC and in particular its AMS extensions.
The development of HW/SW/AMS systems demands for very powerful means for verification.
SystemC is a free discrete event simulator for hardware/software systems.
The particular challenge is to bring circuit level effects to the system level, and to show that the non-idealities have no relevant impact on the system performances.  
SystemC AMS introduces various models of computation, including timed data-flow.  
 
This permits the modelling of signal processing systems, but as well of analog/mixed-signal systems at a high level of abstraction.
Indeed, this challenge can be mastered perfectly with free tools:
We will show how to use SystemC (AMS, TLM) in a hierarchical design and verification flow.
* SystemC, a free discrete event simulator for hardware/software systems.
We show its integration  with circuit level simulation at one hand.
* SystemC AMS, an extension that introduces various models of computation, including timed data-flow. 
At the other hand, we will show integration with system level development processes.
* AADDlib and AADDsim that provide means for symbolic simulation to SystemC and SystemC AMS.
Together, these tools cover design of signal processing and analog/mixed-signal systems.
 
The presentation will show how to use SystemC (AMS, TLM) in a hierarchical design and verification flow.
The flow links circuit level simulation and system level simulation via the characterization of ''properties''.
For characterization, we use Affine Forms of AADDlib that represent nominal value, dependencies, and guarantee safe inclusions.
The properties are then used at a system level simulation with SystemC AMS.
The hierarchical verification flow is supported by the AADDlib that allows the symbolic simulation of SystemC and SystemC AMS.
 
SystemC is available for download under
https://accellera.org/downloads/standards/systemc
 
SystemC AMS is available for download under
https://www.coseda-tech.com/systemc-ams-proof-of-concept
 
AADDlib/AADDsim are available under
https://github.com/TUK-CPS/AADD

Revision as of 02:17, 14 March 2019

The development of HW/SW/AMS systems demands for very powerful means for verification. The particular challenge is to bring circuit level effects to the system level, and to show that the non-idealities have no relevant impact on the system performances.

Indeed, this challenge can be mastered perfectly with free tools:

  • SystemC, a free discrete event simulator for hardware/software systems.
  • SystemC AMS, an extension that introduces various models of computation, including timed data-flow.
  • AADDlib and AADDsim that provide means for symbolic simulation to SystemC and SystemC AMS.

Together, these tools cover design of signal processing and analog/mixed-signal systems.

The presentation will show how to use SystemC (AMS, TLM) in a hierarchical design and verification flow. The flow links circuit level simulation and system level simulation via the characterization of properties. For characterization, we use Affine Forms of AADDlib that represent nominal value, dependencies, and guarantee safe inclusions. The properties are then used at a system level simulation with SystemC AMS. The hierarchical verification flow is supported by the AADDlib that allows the symbolic simulation of SystemC and SystemC AMS.

SystemC is available for download under https://accellera.org/downloads/standards/systemc

SystemC AMS is available for download under https://www.coseda-tech.com/systemc-ams-proof-of-concept

AADDlib/AADDsim are available under https://github.com/TUK-CPS/AADD

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