Difference between revisions of "SystemC AMS and upcoming free frameworks for the free design"
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(Created page with "This talk will introduce the SystemC AMS simulator. We will show how to use it in the context of a hierarchical design and verification flow. We show its integration with ci...") |
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This talk will introduce | This talk will introduce SystemC and in particular its AMS extensions. | ||
We will show how to use | SystemC is a free discrete event simulator for hardware/software systems. | ||
SystemC AMS introduces various models of computation, including timed data-flow. | |||
This permits the modelling of signal processing systems, but as well of analog/mixed-signal systems at a high level of abstraction. | |||
We will show how to use SystemC (AMS, TLM) in a hierarchical design and verification flow. | |||
We show its integration with circuit level simulation at one hand. | We show its integration with circuit level simulation at one hand. | ||
At the other hand, we will show integration with system level development processes. | At the other hand, we will show integration with system level development processes. |
Revision as of 15:19, 11 March 2019
This talk will introduce SystemC and in particular its AMS extensions. SystemC is a free discrete event simulator for hardware/software systems. SystemC AMS introduces various models of computation, including timed data-flow. This permits the modelling of signal processing systems, but as well of analog/mixed-signal systems at a high level of abstraction. We will show how to use SystemC (AMS, TLM) in a hierarchical design and verification flow. We show its integration with circuit level simulation at one hand. At the other hand, we will show integration with system level development processes.