Difference between revisions of "Standard-cell recognition"

From F-Si wiki
Jump to navigation Jump to search
Line 1: Line 1:
Standard-cell recognition or 'functional abstraction' refers to the process of automatically deducing the abstract logical behavior of a CMOS circuit based on the transistor-level netlist. This methods find applications in verification, reverse engineering and automated design tools such as tools for [[Standard-cell characterization]].
Standard-cell recognition or 'functional abstraction' refers to the process of automatically deducing the abstract logical behavior of a CMOS circuit based on the transistor-level netlist. This methods find applications in verification, reverse engineering and automated design tools such as tools for [[Standard-cell characterization]].
=Algorithms=
An algorithm for CMOS functional abstraction can be found in <ref name="yagle" />.


==Recognizing combinational CMOS logic==
==Recognizing combinational CMOS logic==
Line 8: Line 12:
Recognizing sequential logic involves detecting the feedback loops and finding their data inputs, outputs and write conditions.
Recognizing sequential logic involves detecting the feedback loops and finding their data inputs, outputs and write conditions.


== FOSS Software ==
* [[LibreCell]] (librecell-lib)


==References==
==References==

Revision as of 22:04, 16 February 2021

Standard-cell recognition or 'functional abstraction' refers to the process of automatically deducing the abstract logical behavior of a CMOS circuit based on the transistor-level netlist. This methods find applications in verification, reverse engineering and automated design tools such as tools for Standard-cell characterization.

Algorithms

An algorithm for CMOS functional abstraction can be found in [1].

Recognizing combinational CMOS logic

TBD

Recognizing sequential CMOS logic

State-full CMOS logic necessarily has feedback loops. A feedback loop can have several characteristic properties: a) It can be stable and keep it's state, b) it can be transparent and copy the state of the input data signal if the write condition is met, c) it can oscillate or cause a short (e.g. an odd-numbers of inverters connected in a circle). Recognizing sequential logic involves detecting the feedback loops and finding their data inputs, outputs and write conditions.

FOSS Software

References

  1. Anthony Lester, Pirouz Bazargan-Sabet, Alain Greiner, YAGLE, a Second generation Functional Abstractor for CMOS VLSI Circuits, https://dx.doi.org/10.1109/ICM.1998.825615