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Showing below up to 62 results in range #1 to #62.

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  1. ABSYNTH: Analog Design Automation - An approach to bring VLSI analog design to the hobbyists/non-professionals
  2. ASICone. Goals, timeline, participants and tools
  3. CERN OHL v2 draft
  4. CERN Open Hardware License (OHL)
  5. CIAN Team Welcome
  6. CMOS functional abstraction
  7. CMP add on services - Towards Foundry PDKs on Free CAD Tools
  8. Converting 45nm transistor netlists to open standards
  9. Coriolis (installation)
  10. Coriolis (tutorials)
  11. Development of FreePDK: An Open-Source Process Design Kit for Advanced Technology Nodes
  12. F-Si Donations
  13. F-Si Statute
  14. FOS standard cell generator from scratch
  15. FSiC2019
  16. FSiC2019 reimbursement
  17. FSiC2019 venue
  18. FSiC2020
  19. FSiC2021
  20. From CMOS transistors to filters - A library of analog schematics with automated sizing
  21. From filters to CMOS transistors - A library of analog schematics with automated sizing
  22. From the RISC-V spec to a low-tech SoC, passing by SpinalHDL, VexRiscv and OpenOCD
  23. GAUT
  24. GAUT - A Free and Open-Source High-Level Synthesis tool
  25. GHDL and the economy of EDA FOSS
  26. GnuCap: Progress and Opportunities
  27. Gnu Circuit Analysis Package (GnuCap)
  28. Guidelines for invited speakers
  29. Hands-on with KLayout: Design rule checks and layout to netlist tools
  30. High level Simulation
  31. High level system modelling, hands-on computer session
  32. Horizon 2021 Coordination and Support Action (CSA) proposal
  33. KLayout's deep verification base project
  34. LIP6 Welcome
  35. Lesson learned from Retro-uC and the search for the ideal EDA flow for open source silicon
  36. LibrEDA
  37. LibreCell
  38. Libre Silicon Compiler
  39. LiteX: an open-source SoC builder and library based on Migen Python DSL
  40. Main Page
  41. Main Page/Software
  42. Matthias:UnsortedThroughsOnFOSSForEDA
  43. Mediawiki template for invited speakers
  44. Mixed-signal system modelling and simulation
  45. Model-Driven Performance Evaluation and Formal Verification for Multi-level Embedded System Design
  46. Need for a free alternative to OpenAccess (by Matthias)
  47. Ngspice - an open source mixed signal circuit simulator
  48. OpenRAM: An Open-Source Memory Compiler
  49. Open Source Parasitic Extraction
  50. Open Source in Healthcare, an hardware approach: the echOpen project case
  51. Placement algorithms for standard cells in Coriolis
  52. Standard-cell characterization
  53. Standard-cell recognition
  54. Standard-cell synthesis
  55. SystemC AMS and upcoming free frameworks for the free design
  56. The Alliance/Coriolis design flow
  57. The Raven chip: First-time silicon success with qflow and efabless
  58. The development of the NSXLIB standard cell scalable library
  59. The open-source and low-cost echo-stethoscope project
  60. Toward a collaborative environment for Open Hardware Design
  61. Towards digital sovereignty by open source (hardware)
  62. White paper for the EC, January 2020

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