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Showing below up to 90 results in range #51 to #140.

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  1. Gdsfactory
  2. GnuCap: Progress and Opportunities
  3. Gnu Circuit Analysis Package (GnuCap)
  4. Go2async: A high-level synthesis tool for asynchronous circuits
  5. Guidelines for speakers
  6. Hands-on with KLayout: Design rule checks and layout to netlist tools
  7. High level Simulation
  8. High level system modelling, hands-on computer session
  9. Horizon 2021 Coordination and Support Action (CSA) proposal
  10. How many designs can you fit on a single die
  11. How to foster GreenIT through open hardware?
  12. Inclusive Modeling with SysMD
  13. Industry-Grade SystemVerilog IPs And The Open Flow: How We Synthesized Iguana
  14. Introduction to the GoIT project
  15. KLayout's deep verification base project
  16. KLayout XSection tool - Deep insights or nonsense in colors?
  17. KQCircuits – open-source EDA software for designing chips with super conducting qubits
  18. KiCad
  19. LIP6 Welcome
  20. Learning from GF180 PDK: Best practices for implementing and optimizing KLayout DRC and LVS decks
  21. Learning hardware design in the video game Minecraft
  22. Lesson learned from Retro-uC and the search for the ideal EDA flow for open source silicon
  23. LibrEDA
  24. LibrEDA - digital place-and-route framework from scratch
  25. LibreCell
  26. Libre Silicon Compiler
  27. LiteX: an open-source SoC builder and library based on Migen Python DSL
  28. Main Page
  29. Main Page/Software
  30. Matthias:UnsortedThroughsOnFOSSForEDA
  31. Merging Gnucap and Qucs -- The Why and How
  32. Mixed-signal system modelling and simulation
  33. Mixing software abstractions for high-level FPGA programming
  34. Model-Driven Performance Evaluation and Formal Verification for Multi-level Embedded System Design
  35. Naja: an open source framework for EDA post synthesis flow development
  36. Naja: project updates and netlist splitting tool
  37. Need for a free alternative to OpenAccess (by Matthias)
  38. Ngspice - an open source mixed signal circuit simulator
  39. Open-source electronic design automation for agile network defense at OVHcloud
  40. OpenEPDA: photonic PDKs with open standards
  41. OpenRAM: An Open-Source Memory Compiler
  42. OpenROAD
  43. OpenSource PDK - A key enabler to unlock the potential of an open source design flow
  44. Open (and Closed) Source Analog Design with Hdl21 & VLSIR
  45. Open Source Parasitic Extraction
  46. Open Source for Sustainable and Long lasting Phones
  47. Open Source in Healthcare, an hardware approach: the echOpen project case
  48. Open source Design Flow status and roadmap for IHP BiCMOS technology
  49. PDKMaster & co.: a framework for scalable and technology portable standard cell, IO and SRAM libraries
  50. Physical security for cryptographic implementations with open hardware
  51. Placement algorithms for standard cells in Coriolis
  52. Porting software to hardware using XLS and open source PDKs
  53. Powered by Open EDA: Applying Apple's Chip-to-Product Design Methods to Satellites
  54. Proof-of-concept for scalable analog blocks using the PDKMaster framework
  55. Recent Developments from YosysHQ
  56. Recommendations and roadmap for the development of open-source silicon in the EU
  57. Recommendations for the EC on how to reduce the environmental impact of the ICT sector
  58. Revolutionize your chip design with GDSFactory and Open Source PDKs
  59. Software-Defined Hardware: Digital Design in the 21st Century with Chisel
  60. Standard-cell characterization
  61. Standard-cell recognition
  62. Standard-cell synthesis
  63. Standard Cell Library report
  64. Statute of the Free Silicon Foundation (I) ETS
  65. Synthesis with ghdl
  66. SystemC AMS and upcoming free frameworks for the free design
  67. Teaching Chip Design with Open-Source Tools
  68. TestPageX
  69. The Alliance/Coriolis design flow
  70. The EPFL Logic Synthesis Libraries: open-source tools for classical and emerging technologies
  71. The Raven chip: First-time silicon success with qflow and efabless
  72. The development of the NSXLIB standard cell scalable library
  73. The importance of EU Academia in developing the chips of the future
  74. The open-source and low-cost echo-stethoscope project
  75. The road to fully open hardware mobile computing
  76. TinyTapeout - what happened and next steps
  77. Toward a collaborative environment for Open Hardware Design
  78. Toward multi-language open-source HDL simulation
  79. Towards digital sovereignty by open source (hardware)
  80. Tutorial and FAQ on physical verification, DRC+LVS
  81. VACASK: a Verilog-A Circuit Analysis Kernel
  82. Verilog-AMS in Gnucap
  83. Verilog-A Circuit Analysis Kernel (VACASK)
  84. Welcome from LIP6
  85. Welcome from the Free Silicon Foundation 2023
  86. White paper for the EC, January 2020
  87. Whom do you trust?: Validating process parameters for open-source tools
  88. Wiki/openic
  89. Wishbone: a free SoC bus family
  90. XSCHEM - circuit schematic editor for VLSI, ASIC, PCB design

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