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Showing below up to 136 results in range #1 to #136.

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  1. 65nm CMOS Design-Flows on Free and Open-Source Tools : An Overview
  2. ABSYNTH: Analog Design Automation - An approach to bring VLSI analog design to the hobbyists/non-professionals
  3. ASICone. Goals, timeline, participants and tools
  4. A Yosys plugin for logic locking
  5. A progressive introduction to memory bus interconnect API in Software-Defined Hardware
  6. Accelerating the Open Source Silicon Ecosystem with Jupyter Notebooks
  7. All you ever wanted to know about side-channel attacks and protections (and a forthcoming book)
  8. An overview of libre silicon and OSHW related efforts within NGI and NLnet
  9. Analyzing open-source chip design ecosystem from an environmental sustainability perspective
  10. Black-tie Python: Formal verification with Amaranth
  11. CERN OHL v2 draft
  12. CERN Open Hardware License (OHL)
  13. CIAN Team Welcome
  14. CMOS functional abstraction
  15. CMP add on services - Towards Foundry PDKs on Free CAD Tools
  16. Challenge to Fabricate LSI without NDA with Open Method
  17. Closing The Synthesis Gap — Is Open Source Logic Synthesis About To Beat The Industry?
  18. Composing an out-of-order CPU using software technics
  19. Converting 45nm transistor netlists to open standards
  20. Coriolis (installation)
  21. Coriolis (tutorials)
  22. Coriolis a RTL to GDSII FOSS Design Flow
  23. Design of a 1.2MS/s Charge-Redistribution Non-Binary SAR-ADC Utilizing the SKY130 Open-Source Technology
  24. Development of FreePDK: An Open-Source Process Design Kit for Advanced Technology Nodes
  25. Digital placement algorithms in Coriolis
  26. E-Waste Reverse Engineering Toolkit (RET)
  27. Environmental impacts of electronics and the role of open source hardware
  28. Exploring open hardware solutions for ensuring the security of RISC-V processors
  29. F-Si Donations
  30. F-Si Statute
  31. F8
  32. FOS standard cell generator from scratch
  33. FSiC2019
  34. FSiC2019 reimbursement
  35. FSiC2019 venue
  36. FSiC2020
  37. FSiC2021
  38. FSiC2022
  39. FSiC2022 venue
  40. FSiC2023
  41. FSiC2023 venue
  42. FSiC2024
  43. Free Silicon Foundation
  44. From CMOS transistors to filters - A library of analog schematics with automated sizing
  45. From filters to CMOS transistors - A library of analog schematics with automated sizing
  46. From the RISC-V spec to a low-tech SoC, passing by SpinalHDL, VexRiscv and OpenOCD
  47. GAUT
  48. GAUT - A Free and Open-Source High-Level Synthesis tool
  49. GHDL and the economy of EDA FOSS
  50. Gdsfactory
  51. GnuCap: Progress and Opportunities
  52. Gnu Circuit Analysis Package (GnuCap)
  53. Go2async: A high-level synthesis tool for asynchronous circuits
  54. Guidelines for invited speakers
  55. Hands-on with KLayout: Design rule checks and layout to netlist tools
  56. High level Simulation
  57. High level system modelling, hands-on computer session
  58. Horizon 2021 Coordination and Support Action (CSA) proposal
  59. How many designs can you fit on a single die
  60. How to foster GreenIT through open hardware?
  61. Inclusive Modeling with SysMD
  62. Industry-Grade SystemVerilog IPs And The Open Flow: How We Synthesized Iguana
  63. Introduction to the GoIT project
  64. KLayout's deep verification base project
  65. KLayout XSection tool - Deep insights or nonsense in colors?
  66. KQCircuits – open-source EDA software for designing chips with super conducting qubits
  67. KiCad
  68. LIP6 Welcome
  69. Learning from GF180 PDK: Best practices for implementing and optimizing KLayout DRC and LVS decks
  70. Learning hardware design in the video game Minecraft
  71. Lesson learned from Retro-uC and the search for the ideal EDA flow for open source silicon
  72. LibrEDA
  73. LibrEDA - digital place-and-route framework from scratch
  74. LibreCell
  75. Libre Silicon Compiler
  76. LiteX: an open-source SoC builder and library based on Migen Python DSL
  77. Main Page
  78. Main Page/Software
  79. Matthias:UnsortedThroughsOnFOSSForEDA
  80. Mediawiki template for invited speakers
  81. Merging Gnucap and Qucs -- The Why and How
  82. Mixed-signal system modelling and simulation
  83. Mixing software abstractions for high-level FPGA programming
  84. Model-Driven Performance Evaluation and Formal Verification for Multi-level Embedded System Design
  85. Naja: an open source framework for EDA post synthesis flow development
  86. Naja: project updates and netlist splitting tool
  87. Need for a free alternative to OpenAccess (by Matthias)
  88. Ngspice - an open source mixed signal circuit simulator
  89. Open-source electronic design automation for agile network defense at OVHcloud
  90. OpenEPDA: photonic PDKs with open standards
  91. OpenRAM: An Open-Source Memory Compiler
  92. OpenROAD
  93. OpenSource PDK - A key enabler to unlock the potential of an open source design flow
  94. Open (and Closed) Source Analog Design with Hdl21 & VLSIR
  95. Open Source Parasitic Extraction
  96. Open Source for Sustainable and Long lasting Phones
  97. Open Source in Healthcare, an hardware approach: the echOpen project case
  98. Open source Design Flow status and roadmap for IHP BiCMOS technology
  99. PDKMaster & co.: a framework for scalable and technology portable standard cell, IO and SRAM libraries
  100. Physical security for cryptographic implementations with open hardware
  101. Placement algorithms for standard cells in Coriolis
  102. Porting software to hardware using XLS and open source PDKs
  103. Powered by Open EDA: Applying Apple's Chip-to-Product Design Methods to Satellites
  104. Proof-of-concept for scalable analog blocks using the PDKMaster framework
  105. Recent Developments from YosysHQ
  106. Recommendations and roadmap for the development of open-source silicon in the EU
  107. Recommendations for the EC on how to reduce the environmental impact of the ICT sector
  108. Software-Defined Hardware: Digital Design in the 21st Century with Chisel
  109. Standard-cell characterization
  110. Standard-cell recognition
  111. Standard-cell synthesis
  112. Standard Cell Library report
  113. Statute of the Free Silicon Foundation (I) ETS
  114. Synthesis with ghdl
  115. SystemC AMS and upcoming free frameworks for the free design
  116. Teaching Chip Design with Open-Source Tools
  117. TestPageX
  118. The Alliance/Coriolis design flow
  119. The Raven chip: First-time silicon success with qflow and efabless
  120. The development of the NSXLIB standard cell scalable library
  121. The importance of EU Academia in developing the chips of the future
  122. The open-source and low-cost echo-stethoscope project
  123. The road to fully open hardware mobile computing
  124. TinyTapeout - what happened and next steps
  125. Toward a collaborative environment for Open Hardware Design
  126. Toward multi-language open-source HDL simulation
  127. Towards digital sovereignty by open source (hardware)
  128. Tutorial and FAQ on physical verification, DRC+LVS
  129. Verilog-AMS in Gnucap
  130. Welcome from LIP6
  131. Welcome from the Free Silicon Foundation 2023
  132. White paper for the EC, January 2020
  133. Whom do you trust?: Validating process parameters for open-source tools
  134. Wiki/openic
  135. Wishbone: a free SoC bus family
  136. XSCHEM - circuit schematic editor for VLSI, ASIC, PCB design

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