Pages without language links
Jump to navigation
Jump to search
The following pages do not link to other language versions.
Showing below up to 136 results in range #1 to #136.
View (previous 250 | next 250) (20 | 50 | 100 | 250 | 500)
- 65nm CMOS Design-Flows on Free and Open-Source Tools : An Overview
- ABSYNTH: Analog Design Automation - An approach to bring VLSI analog design to the hobbyists/non-professionals
- ASICone. Goals, timeline, participants and tools
- A Yosys plugin for logic locking
- A progressive introduction to memory bus interconnect API in Software-Defined Hardware
- Accelerating the Open Source Silicon Ecosystem with Jupyter Notebooks
- All you ever wanted to know about side-channel attacks and protections (and a forthcoming book)
- An overview of libre silicon and OSHW related efforts within NGI and NLnet
- Analyzing open-source chip design ecosystem from an environmental sustainability perspective
- Black-tie Python: Formal verification with Amaranth
- CERN OHL v2 draft
- CERN Open Hardware License (OHL)
- CIAN Team Welcome
- CMOS functional abstraction
- CMP add on services - Towards Foundry PDKs on Free CAD Tools
- Challenge to Fabricate LSI without NDA with Open Method
- Closing The Synthesis Gap — Is Open Source Logic Synthesis About To Beat The Industry?
- Composing an out-of-order CPU using software technics
- Converting 45nm transistor netlists to open standards
- Coriolis (installation)
- Coriolis (tutorials)
- Coriolis a RTL to GDSII FOSS Design Flow
- Design of a 1.2MS/s Charge-Redistribution Non-Binary SAR-ADC Utilizing the SKY130 Open-Source Technology
- Development of FreePDK: An Open-Source Process Design Kit for Advanced Technology Nodes
- Digital placement algorithms in Coriolis
- E-Waste Reverse Engineering Toolkit (RET)
- Environmental impacts of electronics and the role of open source hardware
- Exploring open hardware solutions for ensuring the security of RISC-V processors
- F-Si Donations
- F-Si Statute
- F8
- FOS standard cell generator from scratch
- FSiC2019
- FSiC2019 reimbursement
- FSiC2019 venue
- FSiC2020
- FSiC2021
- FSiC2022
- FSiC2022 venue
- FSiC2023
- FSiC2023 venue
- FSiC2024
- Free Silicon Foundation
- From CMOS transistors to filters - A library of analog schematics with automated sizing
- From filters to CMOS transistors - A library of analog schematics with automated sizing
- From the RISC-V spec to a low-tech SoC, passing by SpinalHDL, VexRiscv and OpenOCD
- GAUT
- GAUT - A Free and Open-Source High-Level Synthesis tool
- GHDL and the economy of EDA FOSS
- Gdsfactory
- GnuCap: Progress and Opportunities
- Gnu Circuit Analysis Package (GnuCap)
- Go2async: A high-level synthesis tool for asynchronous circuits
- Guidelines for invited speakers
- Hands-on with KLayout: Design rule checks and layout to netlist tools
- High level Simulation
- High level system modelling, hands-on computer session
- Horizon 2021 Coordination and Support Action (CSA) proposal
- How many designs can you fit on a single die
- How to foster GreenIT through open hardware?
- Inclusive Modeling with SysMD
- Industry-Grade SystemVerilog IPs And The Open Flow: How We Synthesized Iguana
- Introduction to the GoIT project
- KLayout's deep verification base project
- KLayout XSection tool - Deep insights or nonsense in colors?
- KQCircuits – open-source EDA software for designing chips with super conducting qubits
- KiCad
- LIP6 Welcome
- Learning from GF180 PDK: Best practices for implementing and optimizing KLayout DRC and LVS decks
- Learning hardware design in the video game Minecraft
- Lesson learned from Retro-uC and the search for the ideal EDA flow for open source silicon
- LibrEDA
- LibrEDA - digital place-and-route framework from scratch
- LibreCell
- Libre Silicon Compiler
- LiteX: an open-source SoC builder and library based on Migen Python DSL
- Main Page
- Main Page/Software
- Matthias:UnsortedThroughsOnFOSSForEDA
- Mediawiki template for invited speakers
- Merging Gnucap and Qucs -- The Why and How
- Mixed-signal system modelling and simulation
- Mixing software abstractions for high-level FPGA programming
- Model-Driven Performance Evaluation and Formal Verification for Multi-level Embedded System Design
- Naja: an open source framework for EDA post synthesis flow development
- Naja: project updates and netlist splitting tool
- Need for a free alternative to OpenAccess (by Matthias)
- Ngspice - an open source mixed signal circuit simulator
- Open-source electronic design automation for agile network defense at OVHcloud
- OpenEPDA: photonic PDKs with open standards
- OpenRAM: An Open-Source Memory Compiler
- OpenROAD
- OpenSource PDK - A key enabler to unlock the potential of an open source design flow
- Open (and Closed) Source Analog Design with Hdl21 & VLSIR
- Open Source Parasitic Extraction
- Open Source for Sustainable and Long lasting Phones
- Open Source in Healthcare, an hardware approach: the echOpen project case
- Open source Design Flow status and roadmap for IHP BiCMOS technology
- PDKMaster & co.: a framework for scalable and technology portable standard cell, IO and SRAM libraries
- Physical security for cryptographic implementations with open hardware
- Placement algorithms for standard cells in Coriolis
- Porting software to hardware using XLS and open source PDKs
- Powered by Open EDA: Applying Apple's Chip-to-Product Design Methods to Satellites
- Proof-of-concept for scalable analog blocks using the PDKMaster framework
- Recent Developments from YosysHQ
- Recommendations and roadmap for the development of open-source silicon in the EU
- Recommendations for the EC on how to reduce the environmental impact of the ICT sector
- Software-Defined Hardware: Digital Design in the 21st Century with Chisel
- Standard-cell characterization
- Standard-cell recognition
- Standard-cell synthesis
- Standard Cell Library report
- Statute of the Free Silicon Foundation (I) ETS
- Synthesis with ghdl
- SystemC AMS and upcoming free frameworks for the free design
- Teaching Chip Design with Open-Source Tools
- TestPageX
- The Alliance/Coriolis design flow
- The Raven chip: First-time silicon success with qflow and efabless
- The development of the NSXLIB standard cell scalable library
- The importance of EU Academia in developing the chips of the future
- The open-source and low-cost echo-stethoscope project
- The road to fully open hardware mobile computing
- TinyTapeout - what happened and next steps
- Toward a collaborative environment for Open Hardware Design
- Toward multi-language open-source HDL simulation
- Towards digital sovereignty by open source (hardware)
- Tutorial and FAQ on physical verification, DRC+LVS
- Verilog-AMS in Gnucap
- Welcome from LIP6
- Welcome from the Free Silicon Foundation 2023
- White paper for the EC, January 2020
- Whom do you trust?: Validating process parameters for open-source tools
- Wiki/openic
- Wishbone: a free SoC bus family
- XSCHEM - circuit schematic editor for VLSI, ASIC, PCB design