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Showing below up to 94 results in range #51 to #144.

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  1. GAUT - A Free and Open-Source High-Level Synthesis tool
  2. GHDL and the economy of EDA FOSS
  3. Gdsfactory
  4. GnuCap: Progress and Opportunities
  5. Gnu Circuit Analysis Package (GnuCap)
  6. Go2async: A high-level synthesis tool for asynchronous circuits
  7. Guidelines for speakers
  8. Hands-on with KLayout: Design rule checks and layout to netlist tools
  9. High level Simulation
  10. High level system modelling, hands-on computer session
  11. Horizon 2021 Coordination and Support Action (CSA) proposal
  12. How many designs can you fit on a single die
  13. How to foster GreenIT through open hardware?
  14. Inclusive Modeling with SysMD
  15. Industry-Grade SystemVerilog IPs And The Open Flow: How We Synthesized Iguana
  16. Introduction to the GoIT project
  17. KLayout's deep verification base project
  18. KLayout XSection tool - Deep insights or nonsense in colors?
  19. KQCircuits – open-source EDA software for designing chips with super conducting qubits
  20. KiCad
  21. LIP6 Welcome
  22. Learning from GF180 PDK: Best practices for implementing and optimizing KLayout DRC and LVS decks
  23. Learning hardware design in the video game Minecraft
  24. Lesson learned from Retro-uC and the search for the ideal EDA flow for open source silicon
  25. LibrEDA
  26. LibrEDA - digital place-and-route framework from scratch
  27. LibreCell
  28. Libre Silicon Compiler
  29. LiteX: an open-source SoC builder and library based on Migen Python DSL
  30. Main Page
  31. Main Page/Software
  32. Matthias:UnsortedThroughsOnFOSSForEDA
  33. Merging Gnucap and Qucs -- The Why and How
  34. Mixed-signal system modelling and simulation
  35. Mixing software abstractions for high-level FPGA programming
  36. Model-Driven Performance Evaluation and Formal Verification for Multi-level Embedded System Design
  37. Naja: an open source framework for EDA post synthesis flow development
  38. Naja: project updates and netlist splitting tool
  39. Need for a free alternative to OpenAccess (by Matthias)
  40. Ngspice - an open source mixed signal circuit simulator
  41. Open-source electronic design automation for agile network defense at OVHcloud
  42. OpenEPDA: photonic PDKs with open standards
  43. OpenRAM: An Open-Source Memory Compiler
  44. OpenROAD
  45. OpenSource PDK - A key enabler to unlock the potential of an open source design flow
  46. Open (and Closed) Source Analog Design with Hdl21 & VLSIR
  47. Open Source Parasitic Extraction
  48. Open Source for Sustainable and Long lasting Phones
  49. Open Source in Healthcare, an hardware approach: the echOpen project case
  50. Open source Design Flow status and roadmap for IHP BiCMOS technology
  51. PDKMaster & co.: a framework for scalable and technology portable standard cell, IO and SRAM libraries
  52. Physical security for cryptographic implementations with open hardware
  53. Placement algorithms for standard cells in Coriolis
  54. Porting software to hardware using XLS and open source PDKs
  55. Powered by Open EDA: Applying Apple's Chip-to-Product Design Methods to Satellites
  56. Proof-of-concept for scalable analog blocks using the PDKMaster framework
  57. Recent Developments from YosysHQ
  58. Recommendations and roadmap for the development of open-source silicon in the EU
  59. Recommendations for the EC on how to reduce the environmental impact of the ICT sector
  60. Revolutionize your chip design with GDSFactory and Open Source PDKs
  61. Software-Defined Hardware: Digital Design in the 21st Century with Chisel
  62. Standard-cell characterization
  63. Standard-cell recognition
  64. Standard-cell synthesis
  65. Standard Cell Library report
  66. Statute of the Free Silicon Foundation (I) ETS
  67. Synthesis with ghdl
  68. SystemC AMS and upcoming free frameworks for the free design
  69. Teaching Chip Design with Open-Source Tools
  70. TestPageX
  71. The ACT EDA flow for asynchronous logic
  72. The Alliance/Coriolis design flow
  73. The EPFL Logic Synthesis Libraries: open-source tools for classical and emerging technologies
  74. The Raven chip: First-time silicon success with qflow and efabless
  75. The development of the NSXLIB standard cell scalable library
  76. The importance of EU Academia in developing the chips of the future
  77. The open-source and low-cost echo-stethoscope project
  78. The road to fully open hardware mobile computing
  79. TinyTapeout - what happened and next steps
  80. Toward a collaborative environment for Open Hardware Design
  81. Toward multi-language open-source HDL simulation
  82. Towards digital sovereignty by open source (hardware)
  83. Tutorial and FAQ on physical verification, DRC+LVS
  84. VACASK: a Verilog-A Circuit Analysis Kernel
  85. Verilog-AMS in Gnucap
  86. Verilog-AMS in Gnucap (2024)
  87. Verilog-A Circuit Analysis Kernel (VACASK)
  88. Welcome from LIP6
  89. Welcome from the Free Silicon Foundation 2023
  90. White paper for the EC, January 2020
  91. Whom do you trust?: Validating process parameters for open-source tools
  92. Wiki/openic
  93. Wishbone: a free SoC bus family
  94. XSCHEM - circuit schematic editor for VLSI, ASIC, PCB design

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