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Showing below up to 144 results in range #1 to #144.

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  1. (hist) ‎CERN Open Hardware License (OHL) ‎[25 bytes]
  2. (hist) ‎LIP6 Welcome ‎[105 bytes]
  3. (hist) ‎CIAN Team Welcome ‎[107 bytes]
  4. (hist) ‎Analyzing open-source chip design ecosystem from an environmental sustainability perspective ‎[153 bytes]
  5. (hist) ‎LiteX: an open-source SoC builder and library based on Migen Python DSL ‎[178 bytes]
  6. (hist) ‎Digital placement algorithms in Coriolis ‎[218 bytes]
  7. (hist) ‎Standard Cell Library report ‎[238 bytes]
  8. (hist) ‎Challenge to Fabricate LSI without NDA with Open Method ‎[244 bytes]
  9. (hist) ‎Towards digital sovereignty by open source (hardware) ‎[258 bytes]
  10. (hist) ‎Gdsfactory ‎[267 bytes]
  11. (hist) ‎F-Si Donations ‎[273 bytes]
  12. (hist) ‎Introduction to the GoIT project ‎[292 bytes]
  13. (hist) ‎Main Page/Software ‎[307 bytes]
  14. (hist) ‎Welcome from LIP6 ‎[333 bytes]
  15. (hist) ‎The ACT EDA flow for asynchronous logic ‎[344 bytes]
  16. (hist) ‎Ngspice - an open source mixed signal circuit simulator ‎[403 bytes]
  17. (hist) ‎FSiC2020 ‎[405 bytes]
  18. (hist) ‎Welcome from the Free Silicon Foundation 2023 ‎[417 bytes]
  19. (hist) ‎GnuCap: Progress and Opportunities ‎[428 bytes]
  20. (hist) ‎An overview of libre silicon and OSHW related efforts within NGI and NLnet ‎[439 bytes]
  21. (hist) ‎FSiC2019 reimbursement ‎[471 bytes]
  22. (hist) ‎Synthesis with ghdl ‎[492 bytes]
  23. (hist) ‎Libre Silicon Compiler ‎[552 bytes]
  24. (hist) ‎Placement algorithms for standard cells in Coriolis ‎[559 bytes]
  25. (hist) ‎How to foster GreenIT through open hardware? ‎[595 bytes]
  26. (hist) ‎LibrEDA ‎[598 bytes]
  27. (hist) ‎The open-source and low-cost echo-stethoscope project ‎[616 bytes]
  28. (hist) ‎Coriolis a RTL to GDSII FOSS Design Flow ‎[639 bytes]
  29. (hist) ‎From the RISC-V spec to a low-tech SoC, passing by SpinalHDL, VexRiscv and OpenOCD ‎[649 bytes]
  30. (hist) ‎GAUT ‎[664 bytes]
  31. (hist) ‎Coriolis (tutorials) ‎[668 bytes]
  32. (hist) ‎The Alliance/Coriolis design flow ‎[672 bytes]
  33. (hist) ‎ASICone. Goals, timeline, participants and tools ‎[722 bytes]
  34. (hist) ‎Naja: project updates and netlist splitting tool ‎[760 bytes]
  35. (hist) ‎Open Source in Healthcare, an hardware approach: the echOpen project case ‎[772 bytes]
  36. (hist) ‎OpenSource PDK - A key enabler to unlock the potential of an open source design flow ‎[772 bytes]
  37. (hist) ‎Toward multi-language open-source HDL simulation ‎[779 bytes]
  38. (hist) ‎Gnu Circuit Analysis Package (GnuCap) ‎[785 bytes]
  39. (hist) ‎Free Silicon Foundation ‎[787 bytes]
  40. (hist) ‎Main Page ‎[789 bytes]
  41. (hist) ‎CMOS functional abstraction ‎[811 bytes]
  42. (hist) ‎LibrEDA - digital place-and-route framework from scratch ‎[819 bytes]
  43. (hist) ‎FSiC2021 ‎[825 bytes]
  44. (hist) ‎OpenROAD ‎[826 bytes]
  45. (hist) ‎LibreCell ‎[831 bytes]
  46. (hist) ‎Wishbone: a free SoC bus family ‎[840 bytes]
  47. (hist) ‎Design of a 1.2MS/s Charge-Redistribution Non-Binary SAR-ADC Utilizing the SKY130 Open-Source Technology ‎[840 bytes]
  48. (hist) ‎Open (and Closed) Source Analog Design with Hdl21 & VLSIR ‎[847 bytes]
  49. (hist) ‎Learning hardware design in the video game Minecraft ‎[873 bytes]
  50. (hist) ‎A Yosys plugin for logic locking ‎[901 bytes]
  51. (hist) ‎Wiki/openic ‎[902 bytes]
  52. (hist) ‎CERN OHL v2 draft ‎[954 bytes]
  53. (hist) ‎GAUT - A Free and Open-Source High-Level Synthesis tool ‎[959 bytes]
  54. (hist) ‎TinyTapeout - what happened and next steps ‎[967 bytes]
  55. (hist) ‎A progressive introduction to memory bus interconnect API in Software-Defined Hardware ‎[971 bytes]
  56. (hist) ‎The road to fully open hardware mobile computing ‎[1,005 bytes]
  57. (hist) ‎Mixed-signal system modelling and simulation ‎[1,030 bytes]
  58. (hist) ‎How many designs can you fit on a single die ‎[1,148 bytes]
  59. (hist) ‎Lesson learned from Retro-uC and the search for the ideal EDA flow for open source silicon ‎[1,166 bytes]
  60. (hist) ‎From Theory to Tape-Out: Chip Design Education with Edu4Chip ‎[1,172 bytes]
  61. (hist) ‎Accelerating the Open Source Silicon Ecosystem with Jupyter Notebooks ‎[1,183 bytes]
  62. (hist) ‎GHDL and the economy of EDA FOSS ‎[1,185 bytes]
  63. (hist) ‎Composing an out-of-order CPU using software technics ‎[1,190 bytes]
  64. (hist) ‎F8 ‎[1,193 bytes]
  65. (hist) ‎XSCHEM - circuit schematic editor for VLSI, ASIC, PCB design ‎[1,205 bytes]
  66. (hist) ‎ABSYNTH: Analog Design Automation - An approach to bring VLSI analog design to the hobbyists/non-professionals ‎[1,221 bytes]
  67. (hist) ‎Verilog-AMS in Gnucap ‎[1,222 bytes]
  68. (hist) ‎Learning from GF180 PDK: Best practices for implementing and optimizing KLayout DRC and LVS decks ‎[1,225 bytes]
  69. (hist) ‎Powered by Open EDA: Applying Apple's Chip-to-Product Design Methods to Satellites ‎[1,271 bytes]
  70. (hist) ‎Porting software to hardware using XLS and open source PDKs ‎[1,321 bytes]
  71. (hist) ‎Whom do you trust?: Validating process parameters for open-source tools ‎[1,363 bytes]
  72. (hist) ‎All you ever wanted to know about side-channel attacks and protections (and a forthcoming book) ‎[1,365 bytes]
  73. (hist) ‎Revolutionize your chip design with GDSFactory and Open Source PDKs ‎[1,371 bytes]
  74. (hist) ‎From CMOS transistors to filters - A library of analog schematics with automated sizing ‎[1,381 bytes]
  75. (hist) ‎Open Source for Sustainable and Long lasting Phones ‎[1,401 bytes]
  76. (hist) ‎Exploring open hardware solutions for ensuring the security of RISC-V processors ‎[1,405 bytes]
  77. (hist) ‎KLayout's deep verification base project ‎[1,423 bytes]
  78. (hist) ‎PDKMaster & co.: a framework for scalable and technology portable standard cell, IO and SRAM libraries ‎[1,440 bytes]
  79. (hist) ‎Naja: an open source framework for EDA post synthesis flow development ‎[1,445 bytes]
  80. (hist) ‎Closing The Synthesis Gap — Is Open Source Logic Synthesis About To Beat The Industry? ‎[1,447 bytes]
  81. (hist) ‎Go2async: A high-level synthesis tool for asynchronous circuits ‎[1,456 bytes]
  82. (hist) ‎Software-Defined Hardware: Digital Design in the 21st Century with Chisel ‎[1,463 bytes]
  83. (hist) ‎Black-tie Python: Formal verification with Amaranth ‎[1,472 bytes]
  84. (hist) ‎Recent Developments from YosysHQ ‎[1,505 bytes]
  85. (hist) ‎The EPFL Logic Synthesis Libraries: open-source tools for classical and emerging technologies ‎[1,536 bytes]
  86. (hist) ‎Mixing software abstractions for high-level FPGA programming ‎[1,540 bytes]
  87. (hist) ‎Standard-cell recognition ‎[1,543 bytes]
  88. (hist) ‎TestPageX ‎[1,585 bytes]
  89. (hist) ‎Teaching Chip Design with Open-Source Tools ‎[1,610 bytes]
  90. (hist) ‎OpenEPDA: photonic PDKs with open standards ‎[1,720 bytes]
  91. (hist) ‎Tutorial and FAQ on physical verification, DRC+LVS ‎[1,728 bytes]
  92. (hist) ‎Toward a collaborative environment for Open Hardware Design ‎[1,735 bytes]
  93. (hist) ‎OpenRAM: An Open-Source Memory Compiler ‎[1,792 bytes]
  94. (hist) ‎Converting 45nm transistor netlists to open standards ‎[1,798 bytes]
  95. (hist) ‎Open source Design Flow status and roadmap for IHP BiCMOS technology ‎[1,823 bytes]
  96. (hist) ‎The Raven chip: First-time silicon success with qflow and efabless ‎[1,824 bytes]
  97. (hist) ‎65nm CMOS Design-Flows on Free and Open-Source Tools : An Overview ‎[1,835 bytes]
  98. (hist) ‎E-Waste Reverse Engineering Toolkit (RET) ‎[1,844 bytes]
  99. (hist) ‎Environmental impacts of electronics and the role of open source hardware ‎[1,879 bytes]
  100. (hist) ‎Industry-Grade SystemVerilog IPs And The Open Flow: How We Synthesized Iguana ‎[1,950 bytes]
  101. (hist) ‎FSiC2019 venue ‎[1,982 bytes]
  102. (hist) ‎Verilog-A Circuit Analysis Kernel (VACASK) ‎[2,000 bytes]
  103. (hist) ‎Development of FreePDK: An Open-Source Process Design Kit for Advanced Technology Nodes ‎[2,043 bytes]
  104. (hist) ‎Model-Driven Performance Evaluation and Formal Verification for Multi-level Embedded System Design ‎[2,058 bytes]
  105. (hist) ‎Inclusive Modeling with SysMD ‎[2,143 bytes]
  106. (hist) ‎KQCircuits – open-source EDA software for designing chips with super conducting qubits ‎[2,158 bytes]
  107. (hist) ‎Proof-of-concept for scalable analog blocks using the PDKMaster framework ‎[2,164 bytes]
  108. (hist) ‎Horizon 2021 Coordination and Support Action (CSA) proposal ‎[2,186 bytes]
  109. (hist) ‎Guidelines for speakers ‎[2,218 bytes]
  110. (hist) ‎Coriolis (installation) ‎[2,232 bytes]
  111. (hist) ‎Degate: The stakes and challenges of silicon reverse engineering ‎[2,280 bytes]
  112. (hist) ‎Verilog-AMS in Gnucap (2024) ‎[2,316 bytes]
  113. (hist) ‎VACASK: a Verilog-A Circuit Analysis Kernel ‎[2,344 bytes]
  114. (hist) ‎KLayout XSection tool - Deep insights or nonsense in colors? ‎[2,351 bytes]
  115. (hist) ‎The development of the NSXLIB standard cell scalable library ‎[2,529 bytes]
  116. (hist) ‎Hands-on with KLayout: Design rule checks and layout to netlist tools ‎[2,540 bytes]
  117. (hist) ‎Open-source electronic design automation for agile network defense at OVHcloud ‎[2,555 bytes]
  118. (hist) ‎FSiC2024 venue ‎[2,576 bytes]
  119. (hist) ‎FSiC2023 venue ‎[2,632 bytes]
  120. (hist) ‎FOS standard cell generator from scratch ‎[2,671 bytes]
  121. (hist) ‎CMP add on services - Towards Foundry PDKs on Free CAD Tools ‎[2,913 bytes]
  122. (hist) ‎High level Simulation ‎[2,916 bytes]
  123. (hist) ‎SystemC AMS and upcoming free frameworks for the free design ‎[2,967 bytes]
  124. (hist) ‎Merging Gnucap and Qucs -- The Why and How ‎[3,157 bytes]
  125. (hist) ‎Matthias:UnsortedThroughsOnFOSSForEDA ‎[3,355 bytes]
  126. (hist) ‎The importance of EU Academia in developing the chips of the future ‎[3,552 bytes]
  127. (hist) ‎Physical security for cryptographic implementations with open hardware ‎[3,822 bytes]
  128. (hist) ‎From filters to CMOS transistors - A library of analog schematics with automated sizing ‎[3,892 bytes]
  129. (hist) ‎Need for a free alternative to OpenAccess (by Matthias) ‎[3,970 bytes]
  130. (hist) ‎FSiC2022 venue ‎[4,571 bytes]
  131. (hist) ‎Recommendations and roadmap for the development of open-source silicon in the EU ‎[5,411 bytes]
  132. (hist) ‎Standard-cell synthesis ‎[6,553 bytes]
  133. (hist) ‎F-Si Statute ‎[6,568 bytes]
  134. (hist) ‎Recommendations for the EC on how to reduce the environmental impact of the ICT sector ‎[7,632 bytes]
  135. (hist) ‎Open Source Parasitic Extraction ‎[8,445 bytes]
  136. (hist) ‎FSiC2024 ‎[10,561 bytes]
  137. (hist) ‎FSiC2019 ‎[11,221 bytes]
  138. (hist) ‎KiCad ‎[11,255 bytes]
  139. (hist) ‎FSiC2022 ‎[13,360 bytes]
  140. (hist) ‎FSiC2023 ‎[13,400 bytes]
  141. (hist) ‎Standard-cell characterization ‎[16,183 bytes]
  142. (hist) ‎White paper for the EC, January 2020 ‎[20,934 bytes]
  143. (hist) ‎High level system modelling, hands-on computer session ‎[24,004 bytes]
  144. (hist) ‎Statute of the Free Silicon Foundation (I) ETS ‎[35,187 bytes]

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