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Showing below up to 86 results in range #51 to #136.
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- (hist) OpenEPDA: photonic PDKs with open standards [1,720 bytes]
- (hist) Teaching Chip Design with Open-Source Tools [1,610 bytes]
- (hist) TestPageX [1,585 bytes]
- (hist) Standard-cell recognition [1,543 bytes]
- (hist) Mixing software abstractions for high-level FPGA programming [1,540 bytes]
- (hist) Recent Developments from YosysHQ [1,505 bytes]
- (hist) Black-tie Python: Formal verification with Amaranth [1,472 bytes]
- (hist) Software-Defined Hardware: Digital Design in the 21st Century with Chisel [1,463 bytes]
- (hist) Go2async: A high-level synthesis tool for asynchronous circuits [1,456 bytes]
- (hist) Closing The Synthesis Gap — Is Open Source Logic Synthesis About To Beat The Industry? [1,447 bytes]
- (hist) Naja: an open source framework for EDA post synthesis flow development [1,445 bytes]
- (hist) PDKMaster & co.: a framework for scalable and technology portable standard cell, IO and SRAM libraries [1,440 bytes]
- (hist) KLayout's deep verification base project [1,423 bytes]
- (hist) Exploring open hardware solutions for ensuring the security of RISC-V processors [1,405 bytes]
- (hist) Open Source for Sustainable and Long lasting Phones [1,401 bytes]
- (hist) From CMOS transistors to filters - A library of analog schematics with automated sizing [1,381 bytes]
- (hist) All you ever wanted to know about side-channel attacks and protections (and a forthcoming book) [1,365 bytes]
- (hist) Whom do you trust?: Validating process parameters for open-source tools [1,363 bytes]
- (hist) Porting software to hardware using XLS and open source PDKs [1,321 bytes]
- (hist) Powered by Open EDA: Applying Apple's Chip-to-Product Design Methods to Satellites [1,271 bytes]
- (hist) Learning from GF180 PDK: Best practices for implementing and optimizing KLayout DRC and LVS decks [1,225 bytes]
- (hist) Verilog-AMS in Gnucap [1,222 bytes]
- (hist) ABSYNTH: Analog Design Automation - An approach to bring VLSI analog design to the hobbyists/non-professionals [1,221 bytes]
- (hist) XSCHEM - circuit schematic editor for VLSI, ASIC, PCB design [1,205 bytes]
- (hist) F8 [1,193 bytes]
- (hist) Composing an out-of-order CPU using software technics [1,190 bytes]
- (hist) GHDL and the economy of EDA FOSS [1,185 bytes]
- (hist) Accelerating the Open Source Silicon Ecosystem with Jupyter Notebooks [1,183 bytes]
- (hist) Lesson learned from Retro-uC and the search for the ideal EDA flow for open source silicon [1,166 bytes]
- (hist) How many designs can you fit on a single die [1,148 bytes]
- (hist) Mixed-signal system modelling and simulation [1,030 bytes]
- (hist) The road to fully open hardware mobile computing [1,005 bytes]
- (hist) A progressive introduction to memory bus interconnect API in Software-Defined Hardware [971 bytes]
- (hist) TinyTapeout - what happened and next steps [967 bytes]
- (hist) GAUT - A Free and Open-Source High-Level Synthesis tool [959 bytes]
- (hist) CERN OHL v2 draft [954 bytes]
- (hist) Wiki/openic [902 bytes]
- (hist) A Yosys plugin for logic locking [901 bytes]
- (hist) Learning hardware design in the video game Minecraft [873 bytes]
- (hist) Open (and Closed) Source Analog Design with Hdl21 & VLSIR [847 bytes]
- (hist) Design of a 1.2MS/s Charge-Redistribution Non-Binary SAR-ADC Utilizing the SKY130 Open-Source Technology [840 bytes]
- (hist) Wishbone: a free SoC bus family [840 bytes]
- (hist) LibreCell [831 bytes]
- (hist) OpenROAD [826 bytes]
- (hist) FSiC2021 [825 bytes]
- (hist) LibrEDA - digital place-and-route framework from scratch [819 bytes]
- (hist) CMOS functional abstraction [811 bytes]
- (hist) Main Page [789 bytes]
- (hist) Free Silicon Foundation [787 bytes]
- (hist) Gnu Circuit Analysis Package (GnuCap) [785 bytes]
- (hist) Toward multi-language open-source HDL simulation [779 bytes]
- (hist) OpenSource PDK - A key enabler to unlock the potential of an open source design flow [772 bytes]
- (hist) Open Source in Healthcare, an hardware approach: the echOpen project case [772 bytes]
- (hist) Naja: project updates and netlist splitting tool [760 bytes]
- (hist) ASICone. Goals, timeline, participants and tools [722 bytes]
- (hist) The Alliance/Coriolis design flow [672 bytes]
- (hist) Coriolis (tutorials) [668 bytes]
- (hist) GAUT [664 bytes]
- (hist) From the RISC-V spec to a low-tech SoC, passing by SpinalHDL, VexRiscv and OpenOCD [649 bytes]
- (hist) Coriolis a RTL to GDSII FOSS Design Flow [639 bytes]
- (hist) The open-source and low-cost echo-stethoscope project [616 bytes]
- (hist) LibrEDA [598 bytes]
- (hist) How to foster GreenIT through open hardware? [595 bytes]
- (hist) Placement algorithms for standard cells in Coriolis [559 bytes]
- (hist) Libre Silicon Compiler [552 bytes]
- (hist) Synthesis with ghdl [492 bytes]
- (hist) FSiC2019 reimbursement [471 bytes]
- (hist) An overview of libre silicon and OSHW related efforts within NGI and NLnet [439 bytes]
- (hist) GnuCap: Progress and Opportunities [428 bytes]
- (hist) Welcome from the Free Silicon Foundation 2023 [417 bytes]
- (hist) FSiC2020 [405 bytes]
- (hist) Ngspice - an open source mixed signal circuit simulator [403 bytes]
- (hist) Welcome from LIP6 [333 bytes]
- (hist) Main Page/Software [307 bytes]
- (hist) Introduction to the GoIT project [292 bytes]
- (hist) F-Si Donations [273 bytes]
- (hist) Gdsfactory [267 bytes]
- (hist) Towards digital sovereignty by open source (hardware) [258 bytes]
- (hist) Challenge to Fabricate LSI without NDA with Open Method [244 bytes]
- (hist) Standard Cell Library report [238 bytes]
- (hist) Digital placement algorithms in Coriolis [218 bytes]
- (hist) LiteX: an open-source SoC builder and library based on Migen Python DSL [178 bytes]
- (hist) Analyzing open-source chip design ecosystem from an environmental sustainability perspective [153 bytes]
- (hist) CIAN Team Welcome [107 bytes]
- (hist) LIP6 Welcome [105 bytes]
- (hist) CERN Open Hardware License (OHL) [25 bytes]