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Showing below up to 20 results in range #1 to #20.

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  1. (hist) ‎High level system modelling, hands-on computer session ‎[24,004 bytes]
  2. (hist) ‎White paper for the EC, January 2020 ‎[20,934 bytes]
  3. (hist) ‎Standard-cell characterization ‎[16,183 bytes]
  4. (hist) ‎FSiC2019 ‎[11,180 bytes]
  5. (hist) ‎Open Source Parasitic Extraction ‎[8,445 bytes]
  6. (hist) ‎Standard-cell synthesis ‎[6,346 bytes]
  7. (hist) ‎F-Si Statute ‎[6,111 bytes]
  8. (hist) ‎Need for a free alternative to OpenAccess (by Matthias) ‎[3,970 bytes]
  9. (hist) ‎From filters to CMOS transistors - A library of analog schematics with automated sizing ‎[3,892 bytes]
  10. (hist) ‎Matthias:UnsortedThroughsOnFOSSForEDA ‎[3,355 bytes]
  11. (hist) ‎SystemC AMS and upcoming free frameworks for the free design ‎[2,967 bytes]
  12. (hist) ‎High level Simulation ‎[2,916 bytes]
  13. (hist) ‎CMP add on services - Towards Foundry PDKs on Free CAD Tools ‎[2,913 bytes]
  14. (hist) ‎FOS standard cell generator from scratch ‎[2,671 bytes]
  15. (hist) ‎Hands-on with KLayout: Design rule checks and layout to netlist tools ‎[2,540 bytes]
  16. (hist) ‎The development of the NSXLIB standard cell scalable library ‎[2,529 bytes]
  17. (hist) ‎Mediawiki template for invited speakers ‎[2,297 bytes]
  18. (hist) ‎Coriolis (installation) ‎[2,232 bytes]
  19. (hist) ‎Guidelines for invited speakers ‎[2,123 bytes]
  20. (hist) ‎Model-Driven Performance Evaluation and Formal Verification for Multi-level Embedded System Design ‎[2,058 bytes]

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