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Showing below up to 62 results in range #1 to #62.

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  1. (hist) ‎High level system modelling, hands-on computer session ‎[24,004 bytes]
  2. (hist) ‎White paper for the EC, January 2020 ‎[20,934 bytes]
  3. (hist) ‎Standard-cell characterization ‎[16,183 bytes]
  4. (hist) ‎FSiC2019 ‎[11,180 bytes]
  5. (hist) ‎Open Source Parasitic Extraction ‎[8,445 bytes]
  6. (hist) ‎Standard-cell synthesis ‎[6,346 bytes]
  7. (hist) ‎F-Si Statute ‎[6,111 bytes]
  8. (hist) ‎Need for a free alternative to OpenAccess (by Matthias) ‎[3,970 bytes]
  9. (hist) ‎From filters to CMOS transistors - A library of analog schematics with automated sizing ‎[3,892 bytes]
  10. (hist) ‎Matthias:UnsortedThroughsOnFOSSForEDA ‎[3,355 bytes]
  11. (hist) ‎SystemC AMS and upcoming free frameworks for the free design ‎[2,967 bytes]
  12. (hist) ‎High level Simulation ‎[2,916 bytes]
  13. (hist) ‎CMP add on services - Towards Foundry PDKs on Free CAD Tools ‎[2,913 bytes]
  14. (hist) ‎FOS standard cell generator from scratch ‎[2,671 bytes]
  15. (hist) ‎Hands-on with KLayout: Design rule checks and layout to netlist tools ‎[2,540 bytes]
  16. (hist) ‎The development of the NSXLIB standard cell scalable library ‎[2,529 bytes]
  17. (hist) ‎Mediawiki template for invited speakers ‎[2,297 bytes]
  18. (hist) ‎Coriolis (installation) ‎[2,232 bytes]
  19. (hist) ‎Guidelines for invited speakers ‎[2,123 bytes]
  20. (hist) ‎Model-Driven Performance Evaluation and Formal Verification for Multi-level Embedded System Design ‎[2,058 bytes]
  21. (hist) ‎Development of FreePDK: An Open-Source Process Design Kit for Advanced Technology Nodes ‎[2,043 bytes]
  22. (hist) ‎FSiC2019 venue ‎[1,982 bytes]
  23. (hist) ‎FSiC2021 ‎[1,959 bytes]
  24. (hist) ‎The Raven chip: First-time silicon success with qflow and efabless ‎[1,824 bytes]
  25. (hist) ‎Converting 45nm transistor netlists to open standards ‎[1,798 bytes]
  26. (hist) ‎OpenRAM: An Open-Source Memory Compiler ‎[1,792 bytes]
  27. (hist) ‎Toward a collaborative environment for Open Hardware Design ‎[1,735 bytes]
  28. (hist) ‎Standard-cell recognition ‎[1,543 bytes]
  29. (hist) ‎KLayout's deep verification base project ‎[1,423 bytes]
  30. (hist) ‎From CMOS transistors to filters - A library of analog schematics with automated sizing ‎[1,381 bytes]
  31. (hist) ‎ABSYNTH: Analog Design Automation - An approach to bring VLSI analog design to the hobbyists/non-professionals ‎[1,221 bytes]
  32. (hist) ‎GHDL and the economy of EDA FOSS ‎[1,185 bytes]
  33. (hist) ‎Lesson learned from Retro-uC and the search for the ideal EDA flow for open source silicon ‎[1,166 bytes]
  34. (hist) ‎Mixed-signal system modelling and simulation ‎[1,030 bytes]
  35. (hist) ‎GAUT - A Free and Open-Source High-Level Synthesis tool ‎[959 bytes]
  36. (hist) ‎CERN OHL v2 draft ‎[954 bytes]
  37. (hist) ‎CMOS functional abstraction ‎[811 bytes]
  38. (hist) ‎Gnu Circuit Analysis Package (GnuCap) ‎[785 bytes]
  39. (hist) ‎Open Source in Healthcare, an hardware approach: the echOpen project case ‎[772 bytes]
  40. (hist) ‎LibreCell ‎[737 bytes]
  41. (hist) ‎ASICone. Goals, timeline, participants and tools ‎[722 bytes]
  42. (hist) ‎The Alliance/Coriolis design flow ‎[672 bytes]
  43. (hist) ‎Coriolis (tutorials) ‎[668 bytes]
  44. (hist) ‎GAUT ‎[664 bytes]
  45. (hist) ‎From the RISC-V spec to a low-tech SoC, passing by SpinalHDL, VexRiscv and OpenOCD ‎[649 bytes]
  46. (hist) ‎FSiC2020 ‎[617 bytes]
  47. (hist) ‎The open-source and low-cost echo-stethoscope project ‎[616 bytes]
  48. (hist) ‎LibrEDA ‎[598 bytes]
  49. (hist) ‎Placement algorithms for standard cells in Coriolis ‎[559 bytes]
  50. (hist) ‎Libre Silicon Compiler ‎[552 bytes]
  51. (hist) ‎FSiC2019 reimbursement ‎[471 bytes]
  52. (hist) ‎GnuCap: Progress and Opportunities ‎[428 bytes]
  53. (hist) ‎Ngspice - an open source mixed signal circuit simulator ‎[403 bytes]
  54. (hist) ‎Main Page/Software ‎[307 bytes]
  55. (hist) ‎F-Si Donations ‎[276 bytes]
  56. (hist) ‎Towards digital sovereignty by open source (hardware) ‎[258 bytes]
  57. (hist) ‎Main Page ‎[232 bytes]
  58. (hist) ‎LiteX: an open-source SoC builder and library based on Migen Python DSL ‎[178 bytes]
  59. (hist) ‎CIAN Team Welcome ‎[107 bytes]
  60. (hist) ‎LIP6 Welcome ‎[105 bytes]
  61. (hist) ‎CERN Open Hardware License (OHL) ‎[25 bytes]
  62. (hist) ‎Horizon 2021 Coordination and Support Action (CSA) proposal ‎[13 bytes]

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