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Showing below up to 50 results in range #51 to #100.

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51. Placement algorithms for standard cells in Coriolis‏‎ (4 revisions)
52. Physical security for cryptographic implementations with open hardware‏‎ (4 revisions)
53. Open Source for Sustainable and Long lasting Phones‏‎ (4 revisions)
54. Lesson learned from Retro-uC and the search for the ideal EDA flow for open source silicon‏‎ (4 revisions)
55. Recommendations and roadmap for the development of open-source silicon in the EU‏‎ (4 revisions)
56. Main Page/Software‏‎ (4 revisions)
57. Go2async: A high-level synthesis tool for asynchronous circuits‏‎ (4 revisions)
58. Open (and Closed) Source Analog Design with Hdl21 & VLSIR‏‎ (4 revisions)
59. Welcome from the Free Silicon Foundation 2023‏‎ (4 revisions)
60. Verilog-AMS in Gnucap‏‎ (4 revisions)
61. Recent Developments from YosysHQ‏‎ (4 revisions)
62. Learning from GF180 PDK: Best practices for implementing and optimizing KLayout DRC and LVS decks‏‎ (5 revisions)
63. CERN OHL v2 draft‏‎ (5 revisions)
64. Standard-cell recognition‏‎ (5 revisions)
65. Whom do you trust?: Validating process parameters for open-source tools‏‎ (5 revisions)
66. Digital placement algorithms in Coriolis‏‎ (5 revisions)
67. White paper for the EC, January 2020‏‎ (5 revisions)
68. Tutorial and FAQ on physical verification, DRC+LVS‏‎ (5 revisions)
69. Proof-of-concept for scalable analog blocks using the PDKMaster framework‏‎ (5 revisions)
70. Towards digital sovereignty by open source (hardware)‏‎ (5 revisions)
71. Exploring open hardware solutions for ensuring the security of RISC-V processors‏‎ (5 revisions)
72. F-Si Donations‏‎ (5 revisions)
73. OpenROAD‏‎ (5 revisions)
74. PDKMaster & co.: a framework for scalable and technology portable standard cell, IO and SRAM libraries‏‎ (5 revisions)
75. Open source Design Flow status and roadmap for IHP BiCMOS technology‏‎ (5 revisions)
76. From the RISC-V spec to a low-tech SoC, passing by SpinalHDL, VexRiscv and OpenOCD‏‎ (5 revisions)
77. The Raven chip: First-time silicon success with qflow and efabless‏‎ (5 revisions)
78. Welcome from LIP6‏‎ (5 revisions)
79. Learning hardware design in the video game Minecraft‏‎ (5 revisions)
80. A Yosys plugin for logic locking‏‎ (5 revisions)
81. GAUT - A Free and Open-Source High-Level Synthesis tool‏‎ (6 revisions)
82. The importance of EU Academia in developing the chips of the future‏‎ (6 revisions)
83. LibrEDA - digital place-and-route framework from scratch‏‎ (6 revisions)
84. Accelerating the Open Source Silicon Ecosystem with Jupyter Notebooks‏‎ (6 revisions)
85. GHDL and the economy of EDA FOSS‏‎ (6 revisions)
86. F8‏‎ (6 revisions)
87. The Alliance/Coriolis design flow‏‎ (6 revisions)
88. ABSYNTH: Analog Design Automation - An approach to bring VLSI analog design to the hobbyists/non-professionals‏‎ (6 revisions)
89. Black-tie Python: Formal verification with Amaranth‏‎ (6 revisions)
90. Gnu Circuit Analysis Package (GnuCap)‏‎ (7 revisions)
91. TinyTapeout - what happened and next steps‏‎ (7 revisions)
92. KQCircuits – open-source EDA software for designing chips with super conducting qubits‏‎ (7 revisions)
93. Challenge to Fabricate LSI without NDA with Open Method‏‎ (7 revisions)
94. Toward a collaborative environment for Open Hardware Design‏‎ (7 revisions)
95. Coriolis (installation)‏‎ (7 revisions)
96. FSiC2021‏‎ (7 revisions)
97. Design of a 1.2MS/s Charge-Redistribution Non-Binary SAR-ADC Utilizing the SKY130 Open-Source Technology‏‎ (7 revisions)
98. Wiki/openic‏‎ (8 revisions)
99. Merging Gnucap and Qucs -- The Why and How‏‎ (8 revisions)
100. Mixed-signal system modelling and simulation‏‎ (8 revisions)

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