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- 17:05, 16 July 2019 diff hist +92 High level system modelling, hands-on computer session →Slides current
- 17:04, 16 July 2019 diff hist −11 Toward a collaborative environment for Open Hardware Design current
- 17:03, 16 July 2019 diff hist −16 Toward a collaborative environment for Open Hardware Design →References
- 17:03, 16 July 2019 diff hist −17 Toward a collaborative environment for Open Hardware Design →Slides
- 17:02, 16 July 2019 diff hist +78 CERN OHL v2 draft current
- 17:01, 16 July 2019 diff hist +90 CERN OHL v2 draft →Slides
- 17:00, 16 July 2019 diff hist +74 FSiC2019 →Back-end flow and algorithms
- 16:59, 16 July 2019 diff hist +36 The Raven chip: First-time silicon success with qflow and efabless →Slides
- 16:58, 16 July 2019 diff hist −15 Open Source Parasitic Extraction current
- 16:57, 16 July 2019 diff hist +33 CMOS functional abstraction current
- 16:57, 16 July 2019 diff hist +139 CMOS functional abstraction
- 16:55, 16 July 2019 diff hist +163 KLayout's deep verification base project →Abstract current
- 16:53, 16 July 2019 diff hist +97 KLayout's deep verification base project
- 16:52, 16 July 2019 diff hist 0 Placement algorithms for standard cells in Coriolis current
- 16:52, 16 July 2019 diff hist +111 Placement algorithms for standard cells in Coriolis
- 16:51, 16 July 2019 diff hist −31 FOS standard cell generator from scratch current
- 16:50, 16 July 2019 diff hist +102 FOS standard cell generator from scratch
- 16:48, 16 July 2019 diff hist −67 OpenRAM: An Open-Source Memory Compiler →General information current
- 16:48, 16 July 2019 diff hist +82 OpenRAM: An Open-Source Memory Compiler
- 16:47, 16 July 2019 diff hist +74 FSiC2019 →Foundries, PDKs and cell libraries
- 16:46, 16 July 2019 diff hist +1 The development of the NSXLIB standard cell scalable library current
- 16:46, 16 July 2019 diff hist +99 The development of the NSXLIB standard cell scalable library
- 16:45, 16 July 2019 diff hist +111 Converting 45nm transistor netlists to open standards current
- 16:44, 16 July 2019 diff hist +100 Development of FreePDK: An Open-Source Process Design Kit for Advanced Technology Nodes current
- 16:43, 16 July 2019 diff hist −3 CMP add on services - Towards Foundry PDKs on Free CAD Tools current
- 16:43, 16 July 2019 diff hist −31 CMP add on services - Towards Foundry PDKs on Free CAD Tools
- 16:43, 16 July 2019 diff hist +262 CMP add on services - Towards Foundry PDKs on Free CAD Tools
- 16:40, 16 July 2019 diff hist +126 Lesson learned from Retro-uC and the search for the ideal EDA flow for open source silicon current
- 16:39, 16 July 2019 diff hist +137 ASICone. Goals, timeline, participants and tools current
- 16:37, 16 July 2019 diff hist +156 Open Source in Healthcare, an hardware approach: the echOpen project case current
- 16:36, 16 July 2019 diff hist +91 GnuCap: Progress and Opportunities current
- 16:35, 16 July 2019 diff hist +93 Gnu Circuit Analysis Package (GnuCap) current
- 16:34, 16 July 2019 diff hist 0 Ngspice - an open source mixed signal circuit simulator →Downloads current
- 16:34, 16 July 2019 diff hist 0 N File:Ngspice FSiC2019.pdf current
- 16:31, 16 July 2019 diff hist −28 Ngspice - an open source mixed signal circuit simulator
- 16:30, 16 July 2019 diff hist −36 Mixed-signal system modelling and simulation →Downloads current
- 16:29, 16 July 2019 diff hist +109 Mixed-signal system modelling and simulation
- 16:28, 16 July 2019 diff hist +7 SystemC AMS and upcoming free frameworks for the free design →Downloads current
- 16:28, 16 July 2019 diff hist +66 SystemC AMS and upcoming free frameworks for the free design
- 16:25, 16 July 2019 diff hist 0 N File:LiteX FSiC2019.pdf current
- 16:25, 16 July 2019 diff hist +178 N LiteX: an open-source SoC builder and library based on Migen Python DSL Created page with "* Speaker: Florent Kermarrec ==Downloads== * Slides * [https://peertube.f-si.org/videos/watch/82509fba-c73e-4c00-92ff-d89e9eb913f2 Video recording]" current
- 16:23, 16 July 2019 diff hist +39 Mediawiki template for invited speakers →Slides
- 16:21, 16 July 2019 diff hist −99 FSiC2019 →High-level digital design (session I)
- 16:19, 16 July 2019 diff hist +74 FSiC2019 →High-level digital design (session I)
- 16:18, 16 July 2019 diff hist +97 From the RISC-V spec to a low-tech SoC, passing by SpinalHDL, VexRiscv and OpenOCD current
- 16:17, 16 July 2019 diff hist +111 Model-Driven Performance Evaluation and Formal Verification for Multi-level Embedded System Design current
- 16:15, 16 July 2019 diff hist +93 High level Simulation current
- 16:13, 16 July 2019 diff hist +79 GHDL and the economy of EDA FOSS current
- 16:11, 16 July 2019 diff hist +12 Towards digital sovereignty by open source (hardware) current
- 16:11, 16 July 2019 diff hist +13 GAUT - A Free and Open-Source High-Level Synthesis tool current