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Showing below up to 143 results in range #1 to #143.

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  1. FSiC2019 reimbursement‏‎ (15:46, 1 February 2019)
  2. Libre Silicon Compiler‏‎ (11:12, 8 February 2019)
  3. From CMOS transistors to filters - A library of analog schematics with automated sizing‏‎ (11:35, 12 February 2019)
  4. The open-source and low-cost echo-stethoscope project‏‎ (17:38, 25 February 2019)
  5. GAUT‏‎ (09:58, 6 March 2019)
  6. CERN Open Hardware License (OHL)‏‎ (12:59, 12 March 2019)
  7. FSiC2019 venue‏‎ (16:59, 15 March 2019)
  8. Main Page/Software‏‎ (13:19, 18 March 2019)
  9. Coriolis (installation)‏‎ (15:06, 18 March 2019)
  10. Coriolis (tutorials)‏‎ (15:07, 18 March 2019)
  11. LIP6 Welcome‏‎ (19:20, 29 March 2019)
  12. CIAN Team Welcome‏‎ (19:23, 29 March 2019)
  13. GAUT - A Free and Open-Source High-Level Synthesis tool‏‎ (17:11, 16 July 2019)
  14. Towards digital sovereignty by open source (hardware)‏‎ (17:11, 16 July 2019)
  15. GHDL and the economy of EDA FOSS‏‎ (17:13, 16 July 2019)
  16. High level Simulation‏‎ (17:15, 16 July 2019)
  17. Model-Driven Performance Evaluation and Formal Verification for Multi-level Embedded System Design‏‎ (17:17, 16 July 2019)
  18. From the RISC-V spec to a low-tech SoC, passing by SpinalHDL, VexRiscv and OpenOCD‏‎ (17:18, 16 July 2019)
  19. LiteX: an open-source SoC builder and library based on Migen Python DSL‏‎ (17:25, 16 July 2019)
  20. SystemC AMS and upcoming free frameworks for the free design‏‎ (17:28, 16 July 2019)
  21. Mixed-signal system modelling and simulation‏‎ (17:30, 16 July 2019)
  22. Ngspice - an open source mixed signal circuit simulator‏‎ (17:34, 16 July 2019)
  23. Gnu Circuit Analysis Package (GnuCap)‏‎ (17:35, 16 July 2019)
  24. GnuCap: Progress and Opportunities‏‎ (17:36, 16 July 2019)
  25. Open Source in Healthcare, an hardware approach: the echOpen project case‏‎ (17:37, 16 July 2019)
  26. ASICone. Goals, timeline, participants and tools‏‎ (17:39, 16 July 2019)
  27. Lesson learned from Retro-uC and the search for the ideal EDA flow for open source silicon‏‎ (17:40, 16 July 2019)
  28. CMP add on services - Towards Foundry PDKs on Free CAD Tools‏‎ (17:43, 16 July 2019)
  29. Development of FreePDK: An Open-Source Process Design Kit for Advanced Technology Nodes‏‎ (17:44, 16 July 2019)
  30. Converting 45nm transistor netlists to open standards‏‎ (17:45, 16 July 2019)
  31. The development of the NSXLIB standard cell scalable library‏‎ (17:46, 16 July 2019)
  32. OpenRAM: An Open-Source Memory Compiler‏‎ (17:48, 16 July 2019)
  33. FOS standard cell generator from scratch‏‎ (17:51, 16 July 2019)
  34. Placement algorithms for standard cells in Coriolis‏‎ (17:52, 16 July 2019)
  35. KLayout's deep verification base project‏‎ (17:55, 16 July 2019)
  36. CMOS functional abstraction‏‎ (17:57, 16 July 2019)
  37. Open Source Parasitic Extraction‏‎ (17:58, 16 July 2019)
  38. CERN OHL v2 draft‏‎ (18:02, 16 July 2019)
  39. Toward a collaborative environment for Open Hardware Design‏‎ (18:04, 16 July 2019)
  40. High level system modelling, hands-on computer session‏‎ (18:05, 16 July 2019)
  41. From filters to CMOS transistors - A library of analog schematics with automated sizing‏‎ (18:06, 16 July 2019)
  42. ABSYNTH: Analog Design Automation - An approach to bring VLSI analog design to the hobbyists/non-professionals‏‎ (18:08, 16 July 2019)
  43. The Alliance/Coriolis design flow‏‎ (18:10, 16 July 2019)
  44. Hands-on with KLayout: Design rule checks and layout to netlist tools‏‎ (18:11, 16 July 2019)
  45. The Raven chip: First-time silicon success with qflow and efabless‏‎ (01:06, 12 November 2019)
  46. Matthias:UnsortedThroughsOnFOSSForEDA‏‎ (14:45, 24 January 2020)
  47. White paper for the EC, January 2020‏‎ (16:49, 3 February 2020)
  48. Need for a free alternative to OpenAccess (by Matthias)‏‎ (22:23, 14 February 2020)
  49. LibrEDA‏‎ (23:54, 12 January 2021)
  50. Standard-cell recognition‏‎ (23:09, 16 February 2021)
  51. Standard-cell characterization‏‎ (18:36, 21 May 2021)
  52. F-Si Statute‏‎ (23:50, 22 December 2021)
  53. FSiC2021‏‎ (12:27, 7 February 2022)
  54. FSiC2020‏‎ (12:28, 7 February 2022)
  55. KiCad‏‎ (15:58, 10 March 2022)
  56. Horizon 2021 Coordination and Support Action (CSA) proposal‏‎ (12:05, 17 June 2022)
  57. F-Si Donations‏‎ (09:41, 23 June 2022)
  58. FSiC2022 venue‏‎ (13:46, 6 July 2022)
  59. XSCHEM - circuit schematic editor for VLSI, ASIC, PCB design‏‎ (12:22, 12 July 2022)
  60. Composing an out-of-order CPU using software technics‏‎ (22:26, 1 August 2022)
  61. Inclusive Modeling with SysMD‏‎ (22:29, 1 August 2022)
  62. Wishbone: a free SoC bus family‏‎ (22:29, 1 August 2022)
  63. Porting software to hardware using XLS and open source PDKs‏‎ (22:31, 1 August 2022)
  64. Synthesis with ghdl‏‎ (22:32, 1 August 2022)
  65. How many designs can you fit on a single die‏‎ (22:33, 1 August 2022)
  66. Standard Cell Library report‏‎ (22:34, 1 August 2022)
  67. Go2async: A high-level synthesis tool for asynchronous circuits‏‎ (22:36, 1 August 2022)
  68. KLayout XSection tool - Deep insights or nonsense in colors?‏‎ (22:37, 1 August 2022)
  69. OpenSource PDK - A key enabler to unlock the potential of an open source design flow‏‎ (22:38, 1 August 2022)
  70. PDKMaster & co.: a framework for scalable and technology portable standard cell, IO and SRAM libraries‏‎ (22:40, 1 August 2022)
  71. Challenge to Fabricate LSI without NDA with Open Method‏‎ (22:42, 1 August 2022)
  72. F8‏‎ (22:47, 1 August 2022)
  73. OpenEPDA: photonic PDKs with open standards‏‎ (22:56, 1 August 2022)
  74. Merging Gnucap and Qucs -- The Why and How‏‎ (22:59, 1 August 2022)
  75. Whom do you trust?: Validating process parameters for open-source tools‏‎ (23:00, 1 August 2022)
  76. LibrEDA - digital place-and-route framework from scratch‏‎ (23:00, 1 August 2022)
  77. Digital placement algorithms in Coriolis‏‎ (23:01, 1 August 2022)
  78. Naja: an open source framework for EDA post synthesis flow development‏‎ (23:02, 1 August 2022)
  79. Tutorial and FAQ on physical verification, DRC+LVS‏‎ (23:05, 1 August 2022)
  80. 65nm CMOS Design-Flows on Free and Open-Source Tools : An Overview‏‎ (11:16, 23 August 2022)
  81. Wiki/openic‏‎ (04:02, 4 September 2022)
  82. LibreCell‏‎ (00:34, 16 December 2022)
  83. Standard-cell synthesis‏‎ (15:48, 2 February 2023)
  84. FSiC2023 venue‏‎ (15:12, 2 July 2023)
  85. TestPageX‏‎ (14:14, 8 July 2023)
  86. Naja: project updates and netlist splitting tool‏‎ (22:32, 9 July 2023)
  87. E-Waste Reverse Engineering Toolkit (RET)‏‎ (00:05, 11 July 2023)
  88. Software-Defined Hardware: Digital Design in the 21st Century with Chisel‏‎ (22:13, 28 July 2023)
  89. A progressive introduction to memory bus interconnect API in Software-Defined Hardware‏‎ (22:14, 28 July 2023)
  90. Mixing software abstractions for high-level FPGA programming‏‎ (22:14, 28 July 2023)
  91. Toward multi-language open-source HDL simulation‏‎ (22:15, 28 July 2023)
  92. Recent Developments from YosysHQ‏‎ (22:15, 28 July 2023)
  93. Closing The Synthesis Gap — Is Open Source Logic Synthesis About To Beat The Industry?‏‎ (22:16, 28 July 2023)
  94. Industry-Grade SystemVerilog IPs And The Open Flow: How We Synthesized Iguana‏‎ (22:16, 28 July 2023)
  95. Proof-of-concept for scalable analog blocks using the PDKMaster framework‏‎ (22:16, 28 July 2023)
  96. Open source Design Flow status and roadmap for IHP BiCMOS technology‏‎ (22:17, 28 July 2023)
  97. TinyTapeout - what happened and next steps‏‎ (22:18, 28 July 2023)
  98. Powered by Open EDA: Applying Apple's Chip-to-Product Design Methods to Satellites‏‎ (22:18, 28 July 2023)
  99. Analyzing open-source chip design ecosystem from an environmental sustainability perspective‏‎ (22:19, 28 July 2023)
  100. Open Source for Sustainable and Long lasting Phones‏‎ (22:19, 28 July 2023)
  101. Open-source electronic design automation for agile network defense at OVHcloud‏‎ (22:20, 28 July 2023)
  102. Physical security for cryptographic implementations with open hardware‏‎ (22:20, 28 July 2023)
  103. Black-tie Python: Formal verification with Amaranth‏‎ (22:21, 28 July 2023)
  104. Exploring open hardware solutions for ensuring the security of RISC-V processors‏‎ (22:21, 28 July 2023)
  105. A Yosys plugin for logic locking‏‎ (22:22, 28 July 2023)
  106. All you ever wanted to know about side-channel attacks and protections (and a forthcoming book)‏‎ (22:22, 28 July 2023)
  107. Design of a 1.2MS/s Charge-Redistribution Non-Binary SAR-ADC Utilizing the SKY130 Open-Source Technology‏‎ (22:22, 28 July 2023)
  108. Verilog-AMS in Gnucap‏‎ (22:23, 28 July 2023)
  109. How to foster GreenIT through open hardware?‏‎ (22:24, 28 July 2023)
  110. The importance of EU Academia in developing the chips of the future‏‎ (22:25, 28 July 2023)
  111. Open (and Closed) Source Analog Design with Hdl21 & VLSIR‏‎ (22:26, 28 July 2023)
  112. An overview of libre silicon and OSHW related efforts within NGI and NLnet‏‎ (22:27, 28 July 2023)
  113. KQCircuits – open-source EDA software for designing chips with super conducting qubits‏‎ (22:28, 28 July 2023)
  114. Coriolis a RTL to GDSII FOSS Design Flow‏‎ (22:28, 28 July 2023)
  115. Learning from GF180 PDK: Best practices for implementing and optimizing KLayout DRC and LVS decks‏‎ (22:29, 28 July 2023)
  116. Teaching Chip Design with Open-Source Tools‏‎ (22:29, 28 July 2023)
  117. Learning hardware design in the video game Minecraft‏‎ (22:29, 28 July 2023)
  118. Accelerating the Open Source Silicon Ecosystem with Jupyter Notebooks‏‎ (22:29, 28 July 2023)
  119. OpenROAD‏‎ (12:09, 11 August 2023)
  120. The road to fully open hardware mobile computing‏‎ (15:08, 24 August 2023)
  121. Introduction to the GoIT project‏‎ (15:11, 24 August 2023)
  122. Welcome from LIP6‏‎ (16:23, 24 August 2023)
  123. Welcome from the Free Silicon Foundation 2023‏‎ (16:24, 24 August 2023)
  124. Recommendations for the EC on how to reduce the environmental impact of the ICT sector‏‎ (22:10, 30 September 2023)
  125. FSiC2023‏‎ (17:08, 1 October 2023)
  126. FSiC2022‏‎ (17:09, 1 October 2023)
  127. FSiC2019‏‎ (17:09, 1 October 2023)
  128. Environmental impacts of electronics and the role of open source hardware‏‎ (16:34, 20 October 2023)
  129. Recommendations and roadmap for the development of open-source silicon in the EU‏‎ (19:13, 3 November 2023)
  130. Main Page‏‎ (17:24, 25 January 2024)
  131. Free Silicon Foundation‏‎ (14:57, 31 January 2024)
  132. Gdsfactory‏‎ (11:21, 6 March 2024)
  133. Statute of the Free Silicon Foundation (I) ETS‏‎ (17:47, 28 March 2024)
  134. FSiC2024 venue‏‎ (17:29, 22 April 2024)
  135. Guidelines for speakers‏‎ (19:17, 22 April 2024)
  136. Revolutionize your chip design with GDSFactory and Open Source PDKs‏‎ (20:49, 22 April 2024)
  137. Verilog-A Circuit Analysis Kernel (VACASK)‏‎ (08:54, 23 April 2024)
  138. The EPFL Logic Synthesis Libraries: open-source tools for classical and emerging technologies‏‎ (09:04, 23 April 2024)
  139. VACASK: a Verilog-A Circuit Analysis Kernel‏‎ (09:23, 23 April 2024)
  140. Degate: The stakes and challenges of silicon reverse engineering‏‎ (19:32, 23 April 2024)
  141. Verilog-AMS in Gnucap (2024)‏‎ (08:59, 24 April 2024)
  142. FSiC2024‏‎ (13:48, 24 April 2024)
  143. From Theory to Tape-Out: Chip Design Education with Edu4Chip‏‎ (15:04, 24 April 2024)

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