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Showing below up to 20 results in range #51 to #70.
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- Standard-cell characterization (18:36, 21 May 2021)
- F-Si Statute (23:50, 22 December 2021)
- FSiC2021 (12:27, 7 February 2022)
- FSiC2020 (12:28, 7 February 2022)
- KiCad (15:58, 10 March 2022)
- Horizon 2021 Coordination and Support Action (CSA) proposal (12:05, 17 June 2022)
- F-Si Donations (09:41, 23 June 2022)
- FSiC2022 venue (13:46, 6 July 2022)
- XSCHEM - circuit schematic editor for VLSI, ASIC, PCB design (12:22, 12 July 2022)
- Composing an out-of-order CPU using software technics (22:26, 1 August 2022)
- Inclusive Modeling with SysMD (22:29, 1 August 2022)
- Wishbone: a free SoC bus family (22:29, 1 August 2022)
- Porting software to hardware using XLS and open source PDKs (22:31, 1 August 2022)
- Synthesis with ghdl (22:32, 1 August 2022)
- How many designs can you fit on a single die (22:33, 1 August 2022)
- Standard Cell Library report (22:34, 1 August 2022)
- Go2async: A high-level synthesis tool for asynchronous circuits (22:36, 1 August 2022)
- KLayout XSection tool - Deep insights or nonsense in colors? (22:37, 1 August 2022)
- OpenSource PDK - A key enabler to unlock the potential of an open source design flow (22:38, 1 August 2022)
- PDKMaster & co.: a framework for scalable and technology portable standard cell, IO and SRAM libraries (22:40, 1 August 2022)