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Showing below up to 20 results in range #21 to #40.
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- Mixed-signal system modelling and simulation (17:30, 16 July 2019)
- Ngspice - an open source mixed signal circuit simulator (17:34, 16 July 2019)
- Gnu Circuit Analysis Package (GnuCap) (17:35, 16 July 2019)
- GnuCap: Progress and Opportunities (17:36, 16 July 2019)
- Open Source in Healthcare, an hardware approach: the echOpen project case (17:37, 16 July 2019)
- ASICone. Goals, timeline, participants and tools (17:39, 16 July 2019)
- Lesson learned from Retro-uC and the search for the ideal EDA flow for open source silicon (17:40, 16 July 2019)
- CMP add on services - Towards Foundry PDKs on Free CAD Tools (17:43, 16 July 2019)
- Development of FreePDK: An Open-Source Process Design Kit for Advanced Technology Nodes (17:44, 16 July 2019)
- Converting 45nm transistor netlists to open standards (17:45, 16 July 2019)
- The development of the NSXLIB standard cell scalable library (17:46, 16 July 2019)
- OpenRAM: An Open-Source Memory Compiler (17:48, 16 July 2019)
- FOS standard cell generator from scratch (17:51, 16 July 2019)
- Placement algorithms for standard cells in Coriolis (17:52, 16 July 2019)
- KLayout's deep verification base project (17:55, 16 July 2019)
- CMOS functional abstraction (17:57, 16 July 2019)
- Open Source Parasitic Extraction (17:58, 16 July 2019)
- CERN OHL v2 draft (18:02, 16 July 2019)
- Toward a collaborative environment for Open Hardware Design (18:04, 16 July 2019)
- High level system modelling, hands-on computer session (18:05, 16 July 2019)