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  1. FSiC2019 reimbursement‏‎ (15:46, 1 February 2019)
  2. Guidelines for invited speakers‏‎ (17:09, 6 February 2019)
  3. Libre Silicon Compiler‏‎ (11:12, 8 February 2019)
  4. From CMOS transistors to filters - A library of analog schematics with automated sizing‏‎ (11:35, 12 February 2019)
  5. The open-source and low-cost echo-stethoscope project‏‎ (17:38, 25 February 2019)
  6. GAUT‏‎ (09:58, 6 March 2019)
  7. CERN Open Hardware License (OHL)‏‎ (12:59, 12 March 2019)
  8. FSiC2019 venue‏‎ (16:59, 15 March 2019)
  9. Main Page/Software‏‎ (13:19, 18 March 2019)
  10. LibreCell‏‎ (13:25, 18 March 2019)
  11. Coriolis (installation)‏‎ (15:06, 18 March 2019)
  12. Coriolis (tutorials)‏‎ (15:07, 18 March 2019)
  13. LIP6 Welcome‏‎ (19:20, 29 March 2019)
  14. CIAN Team Welcome‏‎ (19:23, 29 March 2019)
  15. GAUT - A Free and Open-Source High-Level Synthesis tool‏‎ (17:11, 16 July 2019)
  16. Towards digital sovereignty by open source (hardware)‏‎ (17:11, 16 July 2019)
  17. GHDL and the economy of EDA FOSS‏‎ (17:13, 16 July 2019)
  18. High level Simulation‏‎ (17:15, 16 July 2019)
  19. Model-Driven Performance Evaluation and Formal Verification for Multi-level Embedded System Design‏‎ (17:17, 16 July 2019)
  20. From the RISC-V spec to a low-tech SoC, passing by SpinalHDL, VexRiscv and OpenOCD‏‎ (17:18, 16 July 2019)

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