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Showing below up to 94 results in range #51 to #144.

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  1. Standard-cell characterization‏‎ (18:36, 21 May 2021)
  2. F-Si Statute‏‎ (23:50, 22 December 2021)
  3. FSiC2021‏‎ (12:27, 7 February 2022)
  4. FSiC2020‏‎ (12:28, 7 February 2022)
  5. KiCad‏‎ (15:58, 10 March 2022)
  6. Horizon 2021 Coordination and Support Action (CSA) proposal‏‎ (12:05, 17 June 2022)
  7. F-Si Donations‏‎ (09:41, 23 June 2022)
  8. FSiC2022 venue‏‎ (13:46, 6 July 2022)
  9. XSCHEM - circuit schematic editor for VLSI, ASIC, PCB design‏‎ (12:22, 12 July 2022)
  10. Composing an out-of-order CPU using software technics‏‎ (22:26, 1 August 2022)
  11. Inclusive Modeling with SysMD‏‎ (22:29, 1 August 2022)
  12. Wishbone: a free SoC bus family‏‎ (22:29, 1 August 2022)
  13. Porting software to hardware using XLS and open source PDKs‏‎ (22:31, 1 August 2022)
  14. Synthesis with ghdl‏‎ (22:32, 1 August 2022)
  15. How many designs can you fit on a single die‏‎ (22:33, 1 August 2022)
  16. Standard Cell Library report‏‎ (22:34, 1 August 2022)
  17. Go2async: A high-level synthesis tool for asynchronous circuits‏‎ (22:36, 1 August 2022)
  18. KLayout XSection tool - Deep insights or nonsense in colors?‏‎ (22:37, 1 August 2022)
  19. OpenSource PDK - A key enabler to unlock the potential of an open source design flow‏‎ (22:38, 1 August 2022)
  20. PDKMaster & co.: a framework for scalable and technology portable standard cell, IO and SRAM libraries‏‎ (22:40, 1 August 2022)
  21. Challenge to Fabricate LSI without NDA with Open Method‏‎ (22:42, 1 August 2022)
  22. F8‏‎ (22:47, 1 August 2022)
  23. OpenEPDA: photonic PDKs with open standards‏‎ (22:56, 1 August 2022)
  24. Merging Gnucap and Qucs -- The Why and How‏‎ (22:59, 1 August 2022)
  25. Whom do you trust?: Validating process parameters for open-source tools‏‎ (23:00, 1 August 2022)
  26. LibrEDA - digital place-and-route framework from scratch‏‎ (23:00, 1 August 2022)
  27. Digital placement algorithms in Coriolis‏‎ (23:01, 1 August 2022)
  28. Naja: an open source framework for EDA post synthesis flow development‏‎ (23:02, 1 August 2022)
  29. Tutorial and FAQ on physical verification, DRC+LVS‏‎ (23:05, 1 August 2022)
  30. 65nm CMOS Design-Flows on Free and Open-Source Tools : An Overview‏‎ (11:16, 23 August 2022)
  31. Wiki/openic‏‎ (04:02, 4 September 2022)
  32. LibreCell‏‎ (00:34, 16 December 2022)
  33. Standard-cell synthesis‏‎ (15:48, 2 February 2023)
  34. FSiC2023 venue‏‎ (15:12, 2 July 2023)
  35. TestPageX‏‎ (14:14, 8 July 2023)
  36. Naja: project updates and netlist splitting tool‏‎ (22:32, 9 July 2023)
  37. E-Waste Reverse Engineering Toolkit (RET)‏‎ (00:05, 11 July 2023)
  38. Software-Defined Hardware: Digital Design in the 21st Century with Chisel‏‎ (22:13, 28 July 2023)
  39. A progressive introduction to memory bus interconnect API in Software-Defined Hardware‏‎ (22:14, 28 July 2023)
  40. Mixing software abstractions for high-level FPGA programming‏‎ (22:14, 28 July 2023)
  41. Toward multi-language open-source HDL simulation‏‎ (22:15, 28 July 2023)
  42. Recent Developments from YosysHQ‏‎ (22:15, 28 July 2023)
  43. Closing The Synthesis Gap — Is Open Source Logic Synthesis About To Beat The Industry?‏‎ (22:16, 28 July 2023)
  44. Industry-Grade SystemVerilog IPs And The Open Flow: How We Synthesized Iguana‏‎ (22:16, 28 July 2023)
  45. Proof-of-concept for scalable analog blocks using the PDKMaster framework‏‎ (22:16, 28 July 2023)
  46. Open source Design Flow status and roadmap for IHP BiCMOS technology‏‎ (22:17, 28 July 2023)
  47. TinyTapeout - what happened and next steps‏‎ (22:18, 28 July 2023)
  48. Powered by Open EDA: Applying Apple's Chip-to-Product Design Methods to Satellites‏‎ (22:18, 28 July 2023)
  49. Analyzing open-source chip design ecosystem from an environmental sustainability perspective‏‎ (22:19, 28 July 2023)
  50. Open Source for Sustainable and Long lasting Phones‏‎ (22:19, 28 July 2023)
  51. Open-source electronic design automation for agile network defense at OVHcloud‏‎ (22:20, 28 July 2023)
  52. Physical security for cryptographic implementations with open hardware‏‎ (22:20, 28 July 2023)
  53. Black-tie Python: Formal verification with Amaranth‏‎ (22:21, 28 July 2023)
  54. Exploring open hardware solutions for ensuring the security of RISC-V processors‏‎ (22:21, 28 July 2023)
  55. A Yosys plugin for logic locking‏‎ (22:22, 28 July 2023)
  56. All you ever wanted to know about side-channel attacks and protections (and a forthcoming book)‏‎ (22:22, 28 July 2023)
  57. Design of a 1.2MS/s Charge-Redistribution Non-Binary SAR-ADC Utilizing the SKY130 Open-Source Technology‏‎ (22:22, 28 July 2023)
  58. Verilog-AMS in Gnucap‏‎ (22:23, 28 July 2023)
  59. How to foster GreenIT through open hardware?‏‎ (22:24, 28 July 2023)
  60. The importance of EU Academia in developing the chips of the future‏‎ (22:25, 28 July 2023)
  61. Open (and Closed) Source Analog Design with Hdl21 & VLSIR‏‎ (22:26, 28 July 2023)
  62. An overview of libre silicon and OSHW related efforts within NGI and NLnet‏‎ (22:27, 28 July 2023)
  63. KQCircuits – open-source EDA software for designing chips with super conducting qubits‏‎ (22:28, 28 July 2023)
  64. Coriolis a RTL to GDSII FOSS Design Flow‏‎ (22:28, 28 July 2023)
  65. Learning from GF180 PDK: Best practices for implementing and optimizing KLayout DRC and LVS decks‏‎ (22:29, 28 July 2023)
  66. Teaching Chip Design with Open-Source Tools‏‎ (22:29, 28 July 2023)
  67. Learning hardware design in the video game Minecraft‏‎ (22:29, 28 July 2023)
  68. Accelerating the Open Source Silicon Ecosystem with Jupyter Notebooks‏‎ (22:29, 28 July 2023)
  69. OpenROAD‏‎ (12:09, 11 August 2023)
  70. The road to fully open hardware mobile computing‏‎ (15:08, 24 August 2023)
  71. Introduction to the GoIT project‏‎ (15:11, 24 August 2023)
  72. Welcome from LIP6‏‎ (16:23, 24 August 2023)
  73. Welcome from the Free Silicon Foundation 2023‏‎ (16:24, 24 August 2023)
  74. Recommendations for the EC on how to reduce the environmental impact of the ICT sector‏‎ (22:10, 30 September 2023)
  75. FSiC2023‏‎ (17:08, 1 October 2023)
  76. FSiC2022‏‎ (17:09, 1 October 2023)
  77. FSiC2019‏‎ (17:09, 1 October 2023)
  78. Environmental impacts of electronics and the role of open source hardware‏‎ (16:34, 20 October 2023)
  79. Recommendations and roadmap for the development of open-source silicon in the EU‏‎ (19:13, 3 November 2023)
  80. Main Page‏‎ (17:24, 25 January 2024)
  81. Free Silicon Foundation‏‎ (14:57, 31 January 2024)
  82. Gdsfactory‏‎ (11:21, 6 March 2024)
  83. Statute of the Free Silicon Foundation (I) ETS‏‎ (17:47, 28 March 2024)
  84. FSiC2024 venue‏‎ (17:29, 22 April 2024)
  85. Guidelines for speakers‏‎ (19:17, 22 April 2024)
  86. Revolutionize your chip design with GDSFactory and Open Source PDKs‏‎ (20:49, 22 April 2024)
  87. Verilog-A Circuit Analysis Kernel (VACASK)‏‎ (08:54, 23 April 2024)
  88. The EPFL Logic Synthesis Libraries: open-source tools for classical and emerging technologies‏‎ (09:04, 23 April 2024)
  89. Degate: The stakes and challenges of silicon reverse engineering‏‎ (19:32, 23 April 2024)
  90. FSiC2024‏‎ (13:48, 24 April 2024)
  91. From Theory to Tape-Out: Chip Design Education with Edu4Chip‏‎ (15:04, 24 April 2024)
  92. The ACT EDA flow for asynchronous logic‏‎ (17:08, 24 April 2024)
  93. VACASK: a Verilog-A Circuit Analysis Kernel‏‎ (15:35, 25 April 2024)
  94. Verilog-AMS in Gnucap (2024)‏‎ (16:09, 25 April 2024)

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