Recent developments in the Verilog-A circuit analysis kernel

• Speaker(s): Árpád Bűrmen
• email: arpad.buermen@fe.uni-lj.si

Downloads

• Slides: File:Fsic2025-v3.pdf
• Video recording

Abstract

Verilog-A Circuit Analysis Kernel (VACASK) is an advanced analog circuit simulator designed with a clean core architecture and a strict separation between analyses and device models. It leverages the OpenVAF-reloaded Verilog-A compiler to build a robust library of device models. Over the past year, VACASK has seen significant advancements in both performance and capabilities.

One key improvement is device evaluation bypassing, which accelerates transient analysis by skipping the evaluation of device instances. This optimization is very effective in analyses where the nonlinear solver uses the previous solution as its starting point. To assess the impact of various algorithmic enhancements, performance accounting has been integrated into VACASK, and we present benchmark results on several circuits ranging from a few elements up to 10000 elements.

Harmonic Balance (HB) analysis has been introduced for both single- and multi-tone excitation. A simple continuation algorithm enhances convergence, while the current equation formulation remains time-domain based. Future plans include implementing a frequency-domain HB formulation and integrating an iterative linear solver.

One of VACASK’s key limitations has been the absence of a SPICE3 device library. However, this gap is now being addressed through the Verilog-A Distiller project. Verilog-A Distiller converts SPICE3 device models written in C into clean Verilog-A code. So far, basic passive components (resistors, capacitors, and inductors) have been successfully converted, along with semiconductor devices such as the level 1 and 3 diode, level 1 and 2 JFET, level 1 MESFET, Gummel-Poon BJT, MOSFET levels 1-3, 6, 9, and BSIM3 v3.3.0. The converted models were validated with Ngspice simulations.

These developments have been accompanied by numerous bug fixes in the OpenVAF-reloaded project, along with several pull requests in the Ngspice project, further strengthening the free circuit simulator ecosystem.

In conclusion, we highlight the most critical features yet to be implemented, and outline a roadmap for the future evolution of VACASK.

Software

General information

• VACASK repository: https://codeberg.org/arpadbuermen/VACASK
• VACASK binary releases: https://fides.fe.uni-lj.si/vacask/download
• OpenVAF-reloaded repository: https://github.com/arpadbuermen/OpenVAF
• OpenVAF-reloaded binary releases: https://fides.fe.uni-lj.si/openvaf/download
• Verilog-A Distiller repository: https://codeberg.org/arpadbuermen/VADistiller

Roadmap

• Conditional netlist blocks, binning, convert IHP OpenPDK & Skywater PDK
• Faster NOISE and XF analyses (adjunct circuit equations)
• Stability analysis (STAB) and S-parameter analysis (SP)
• Transient noise analysis
• Parallel evaluation (OpenMP)
• Use a parallel linear solver for shared memory systems (MUMPS, SUPERLU)
• Shooting (PSS) & small-signal family (PAC, PXF, PNOISE, PSP, PSTAB)
• Improve harmonic balance, use FFTW library
• HB periodic small-signal family (HBAC, HBXF, HBNOISE, HBSP, HBSTAB)
• Support convolutional linear models (defined in frequency domain, i.e. touchstone files)
• The project seeks funding