Progress on Verilog-AMS support in Gnucap
- Speaker: Felix Salfelder
- email: felix AT salfelder DOT org
Downloads
Abstract
Gnucap is a modern and free/libre mixed signal circuit simulator. It is implemented as a modular C++ library with plugins for commands, algorithms, languages, and device models and wrappers for code written for other projects. Verilog-AMS is a standardised circuit description language adding analog and mixed signal features to the IEEE1364 industry standard aka. Verilog. This talk will cover the status of Verilog-AMS in Gnucap.
Gnucap provides plugins for basic logic gates and "Spice primitives" according to the standard. Modelgen-Verilog transforms Verilog-AMS behavioural models into plugin code. We now support user defined primitives for basic logic modelling, as well as most of Verilog-A. Verilog-A is the analog subset of Verilog-AMS and encompasses analog filter functions, event control and device state.
The structural subset of Verilog describes the representation of circuits, stored as netlists. Gnucap can read, write, edit or simulate Verilog netlists with attributes following the standard. Schematics are circuits with markup attributes added for screen positioning. We have developped a generic tool independent approach to such markup. We present proof-of-concept implementations demonstrating lossless roundtrips from/to existing schematic formats.
Software
General information
- Repository: main, mirror
- Examples: getting started, gnucap examples, modelgen examples
- Plugins: language support, simulator plugins, primitives, foreign models
- Tests: gnucap tests, modelgen tests
- Data exchange: wiki, geda, qucs
- Projects: NLnet'23, Nlnet'24, yours?
Roadmap
- Work in progress on more support for "digital Verilog" and improved compatibility with Spice.
- Fold in new algorithmic enhancements currently under test.
- Gnucap wishes to interface with tools supporting real standards.
- The project seeks help on: testing, packaging, device modelling, QA.