Open (and Closed) Source Analog Design with Hdl21 & VLSIR

• Speaker(s): Dan Fritchman
• email: dan_fritchman@berkeley.edu

Slides - https://docs.google.com/presentation/d/e/2PACX-1vR6rI6Ieo0uReCQQKMKHoDfryybcheYG865Hoc4F012OaSupM3KU1pUdnm1dQWplJrlKjgh2UxxlCY1/pub?start=false&loop=false&delayms=3000&slide=id.g1058543f559_0_0

• Hdl21 - Analog HDL in Python - https://github.com/dan-fritchman/Hdl21
• Hdl21 Schematics - https://github.com/vlsir/hdl21schematics
• Hdl21 Schematic Demos - https://github.com/vlsir/Hdl21schematicDemos
• VLSIR - ProtoBuf-Based Interchange Formats for Chip Design - https://github.com/vlsir/vlsir
• Layout21 - https://github.com/dan-fritchman/Layout21
• Tape-Out Course: Silicon in a Semester - https://ieeexplore.ieee.org/document/9805608