Open (and Closed) Source Analog Design with Hdl21 & VLSIR
Revision as of 19:51, 28 June 2023 by Dan fritchman (talk | contribs) (Created page with " * Speaker(s): Dan Fritchman * email: dan_fritchman@berkeley.edu ==Downloads== * Coming soon! ==Abstract== Coming soon! ==Software== * Hdl21 - Analog HDL in Python - https:...")
- Speaker(s): Dan Fritchman
- email: dan_fritchman@berkeley.edu
Downloads
- Coming soon!
Abstract
Coming soon!
Software
- Hdl21 - Analog HDL in Python - https://github.com/dan-fritchman/Hdl21
- VLSIR - ProtoBuf-Based Interchange Formats for Chip Design - https://github.com/vlsir/vlsir
- Hdl21 Schematics - https://github.com/vlsir/hdl21schematics