Difference between revisions of "OpenRAM: An Open-Source Memory Compiler"

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== Abstract ==
== Abstract ==
[https://github.com/VLSIDA/OpenRAM OpenRAM] is an open-source Python framework to create the layout, netlists, timing and power models, placement and routing models, and other views necessary to use SRAMs in ASIC design. OpenRAM supports integration in both commercial and open-source flows with both predictive and fabricable technologies.
[https://github.com/VLSIDA/OpenRAM OpenRAM] is an open-source Python framework to create the layout, netlists, timing and power models, placement and routing models, and other views necessary to use SRAMs in ASIC design. OpenRAM supports integration in both commercial and open-source flows with both predictive and fabricable technologies.
==Software==
===General information===
* Repository: https://vlsida.github.io/OpenRAM/ https://github.com/VLSIDA/OpenRAM
* Main documentation website: [[OpenRAM Documentation|https://docs.google.com/presentation/d/10InGB33N51I6oBHnqpU7_w9DXlx-qe9zdrlco2Yc5co/edit?usp=sharing]]
* Wikipedia page:
* Wiki page on wiki.f-si.org: https://wiki.f-si.org/index.php/XXX-YYY-ZZZ
===Roadmap===
* The project seeks help on: FinFET memories, Designer Feedback, Other types of memories (CAMs, RFs, etc.)

Revision as of 21:49, 11 March 2019

Slides

File:OpenRAM FSiC2019.pdf

Abstract

OpenRAM is an open-source Python framework to create the layout, netlists, timing and power models, placement and routing models, and other views necessary to use SRAMs in ASIC design. OpenRAM supports integration in both commercial and open-source flows with both predictive and fabricable technologies.

Software

General information

Roadmap

  • The project seeks help on: FinFET memories, Designer Feedback, Other types of memories (CAMs, RFs, etc.)