Difference between revisions of "OpenRAM: An Open-Source Memory Compiler"
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(Created page with "[https://github.com/VLSIDA/OpenRAM OpenRAM] is an open-source Python framework to create the layout, netlists, timing and power models, placement and routing models, and other...") |
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* Speaker: Matthew Guthaus | |||
* Email: mrg@ucsc.edu | |||
* Other information: https://vlsida.github.io/OpenRAM/ https://github.com/VLSIDA/OpenRAM | |||
== Slides == | |||
[[File:OpenRAM FSiC2019.pdf|OpenRAM_FSiC2019.pdf]] | |||
== Abstract == | |||
[https://github.com/VLSIDA/OpenRAM OpenRAM] is an open-source Python framework to create the layout, netlists, timing and power models, placement and routing models, and other views necessary to use SRAMs in ASIC design. OpenRAM supports integration in both commercial and open-source flows with both predictive and fabricable technologies. | [https://github.com/VLSIDA/OpenRAM OpenRAM] is an open-source Python framework to create the layout, netlists, timing and power models, placement and routing models, and other views necessary to use SRAMs in ASIC design. OpenRAM supports integration in both commercial and open-source flows with both predictive and fabricable technologies. | ||
Revision as of 22:45, 11 March 2019
- Speaker: Matthew Guthaus
- Email: mrg@ucsc.edu
- Other information: https://vlsida.github.io/OpenRAM/ https://github.com/VLSIDA/OpenRAM
Slides
Abstract
OpenRAM is an open-source Python framework to create the layout, netlists, timing and power models, placement and routing models, and other views necessary to use SRAMs in ASIC design. OpenRAM supports integration in both commercial and open-source flows with both predictive and fabricable technologies.