Difference between revisions of "Open-source electronic design automation for agile network defense at OVHcloud"
(Created page with " * Speaker(s): Jean Bruant * email: jean [dot] bruant (at) ovhcloud [dot] com ==Downloads== <!-- * Slides (to upload a file: go to Edit mode, then cli...") |
|||
| Line 1: | Line 1: | ||
* Speaker: Jean Bruant | |||
* Speaker | |||
* email: jean [dot] bruant (at) ovhcloud [dot] com | * email: jean [dot] bruant (at) ovhcloud [dot] com | ||
<!-- | |||
==Downloads== | ==Downloads== | ||
* [[:File:File_name.pdf|Slides]] (to upload a file: go to Edit mode, then click on the fourth icon from the left "Embed file" and follow the instructions) | * [[:File:File_name.pdf|Slides]] (to upload a file: go to Edit mode, then click on the fourth icon from the left "Embed file" and follow the instructions) | ||
TBU | |||
--> | --> | ||
==Abstract== | ==Abstract== | ||
In a context of ever-growing worldwide communication traffic and fast deployment of IoT devices, network attacks have become a daily challenge with record-breaking throughput levels. | |||
Fast iterations are decisive to successfully mitigate the threat posed by these attacks. | |||
Compared to software solutions based on general purpose CPUs, FPGA-based mitigation appliances appear as an energy-efficient alternative which combines configurability with guaranteed high-throughput and low-latency. | |||
However, implementation of such dedicated hardware accelerators based on the register-transfer level (RTL) abstraction is a much slower and tedious process than functionally equivalent software developments. | |||
This talk details how open-source EDA tools help with the design and maintenance of agile FPGA-based network defense systems at OVHcloud. | |||
As a key enabler, Hardware Construction Languages (HCLs), such as the Scala-embedded Chisel, apply some existing software abstractions to hardware design, which permits descriptions of circuit generators with high-level software paradigms, such as object-oriented and functional programming. | |||
We first exhibit the relevance of such software inherited paradigms to develop highly re-usable network functions, inspecting both implementation and design perspectives. | |||
Then, we review the associated open-source EDA ecosystem and the integration ability of these novel design methodologies within existing HDL hierarchies. | |||
In particular, we developed an (almost) word-for-word translation of SystemVerilog HDL to Chisel HCL and tools to smoothen the integration of Chisel-generated IPs into SystemVerilog hierarchies. | |||
These open-source tools are available at github.com/ovh/sv2chisel. | |||
==Software== | ==Software== | ||
| Line 20: | Line 27: | ||
* The software has been used in the following projects: Internal OVHcloud projects, maybe elsewhere? Let us know! | * The software has been used in the following projects: Internal OVHcloud projects, maybe elsewhere? Let us know! | ||
===Roadmap=== | ===Roadmap=== | ||
* | * We are currently working on a Chisel-based Pipeline Automation Framework that we aim at releasing as open-source in the near future. | ||
* | * We still seek help on VHDL front-end for sv2chisel to hopefully help with adoption of Chisel in Europe! | ||
- | |||
Revision as of 14:43, 10 July 2023
- Speaker: Jean Bruant
- email: jean [dot] bruant (at) ovhcloud [dot] com
Abstract
In a context of ever-growing worldwide communication traffic and fast deployment of IoT devices, network attacks have become a daily challenge with record-breaking throughput levels. Fast iterations are decisive to successfully mitigate the threat posed by these attacks. Compared to software solutions based on general purpose CPUs, FPGA-based mitigation appliances appear as an energy-efficient alternative which combines configurability with guaranteed high-throughput and low-latency. However, implementation of such dedicated hardware accelerators based on the register-transfer level (RTL) abstraction is a much slower and tedious process than functionally equivalent software developments.
This talk details how open-source EDA tools help with the design and maintenance of agile FPGA-based network defense systems at OVHcloud. As a key enabler, Hardware Construction Languages (HCLs), such as the Scala-embedded Chisel, apply some existing software abstractions to hardware design, which permits descriptions of circuit generators with high-level software paradigms, such as object-oriented and functional programming. We first exhibit the relevance of such software inherited paradigms to develop highly re-usable network functions, inspecting both implementation and design perspectives. Then, we review the associated open-source EDA ecosystem and the integration ability of these novel design methodologies within existing HDL hierarchies. In particular, we developed an (almost) word-for-word translation of SystemVerilog HDL to Chisel HCL and tools to smoothen the integration of Chisel-generated IPs into SystemVerilog hierarchies. These open-source tools are available at github.com/ovh/sv2chisel.
Software
General information
- Repository: https://github.com/ovh/sv2chisel
- The software has been used in the following projects: Internal OVHcloud projects, maybe elsewhere? Let us know!
Roadmap
- We are currently working on a Chisel-based Pipeline Automation Framework that we aim at releasing as open-source in the near future.
- We still seek help on VHDL front-end for sv2chisel to hopefully help with adoption of Chisel in Europe!