Moving toward VexiiRiscv

• Speaker: Charles Papon
• email: charles.papon.90@gmail.com

Downloads

• Slides
• Video recording

Abstract

There is still very few free/open-source/multiple issue/in-order RISC-V CPU in the wild. In the same time, VexRiscv accumulated quite some technical debt and limitations. So it was time to fill those gaps !

VexiiRiscv aim at :

• Providing a free/open-source CPU which can scale from simple micro controller, up to linux ready multi-core / multi-issue cluster (Cortex A53/A55 like)
• Covering both 32 bits and 64 bits RISC-V + IMAFDC + B
• Being very modular and extendable
• Being Debian capable

This talk should normaly run on the hardware itself (FPGA), minus maybe, some kernel panics.

Hardware

General information

• Repository: https://github.com/SpinalHDL/VexiiRiscv
• Main documentation website: https://spinalhdl.github.io/VexiiRiscv-RTD/master/index.html

Roadmap

• The project seeks help on: https://github.com/SpinalHDL/VexiiRiscv/issues/1