Model-Driven Performance Evaluation and Formal Verification for Multi-level Embedded System Design
- Speaker(s): Daniela Genius
- email: daniela.genius@lip6.fr
- Sorbonne Université, LIP6
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Abstract
The design methodology of an embedded system should start with a system-level partitioning dividing functions into hardware and software. However, since this partitioning decision is taken at a high level of abstraction, we propose regularly validating the selected partitioning during software development. We introduce a new model-based engineering process with a supporting toolkit, first performing system-level partitioning, and then assessing the partitioning choices thus obtained at different levels of abstraction during software design. This assessment shall in particular validate the assumptions made on system-level (e.g. on cache miss rates) that cannot be precisely determined without low-level hardware model. This sequence of partitioning and prototyping serves two purposes: validating the assumptions made on system-level, and, while developing the software, taking into account the problematic cases (bus congestion, ping-pong caches etc.) which cannot be detected without precisely simulating the underlying hardware. High-level partitioning simulations/verification rely on custom model-checkers and abstract models of software and hardware, while low-level prototyping simulations rely on automatically generated C-POSIX software code executing on a cycle-precise virtual prototyping platform. An automotive case study on an automatic braking application illustrates our complete approach.
Software
General information
- Contact: https://ttool.telecom-paristech.fr/contact.html
- Repository: https://gitlab.telecom-paristech.fr/mbe-tools/TTool/
- Main documentation website: https://ttool.telecom-paristech.fr/index.html
Roadmap
- The software wishes to interface with the following tools: SystemC AMS
References
- Ludovic Aprville'page: https://perso.telecom-paristech.fr/apvrille/research.html