Difference between revisions of "LibreCell"
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LibreCell is a toolbox for automated CMOS standard-cell synthesis. It's mainly focused on automated layout generation and timing characterization. The goal of the project is to generate a full standard-cell library based on abstract descriptions of the cells (e.g. netlists) and design rules of the target technology. | LibreCell is a toolbox for automated CMOS [[Standard-cell synthesis|standard-cell synthesis]]. It's mainly focused on automated layout generation and [[Standard-cell characterization|timing characterization]]. The goal of the project is to generate a full standard-cell library based on abstract descriptions of the cells (e.g. netlists) and design rules of the target technology. | ||
Revision as of 13:13, 18 March 2019
| Original author(s) | Thomas Kramer |
|---|---|
| Repository | https://codeberg.org/tok/librecell |
| Written in | Python |
| Operating system | Linux |
| Type | Electronic Design Automation (EDA) |
| License | AGPLv3 / CERN OHL-S v2 |
| Website | https://codeberg.org/tok/librecell |
LibreCell is a toolbox for automated CMOS standard-cell synthesis. It's mainly focused on automated layout generation and timing characterization. The goal of the project is to generate a full standard-cell library based on abstract descriptions of the cells (e.g. netlists) and design rules of the target technology.