View source for Greyhound: A RISC-V SoC with tightly coupled eFPGA on IHP SG13G2

* Speaker(s): Leo Moser
* email: leo.moser@pm.me

==Downloads==
* Slides: [[File:FSiC2025 - Greyhound.pdf|thumb]]

==Abstract==

Greyhound, the first open-source RISC-V SoC with tightly coupled eFPGA in the IHP SG13G2 130nm BiCMOS process. 
Greyhound utilizes the full FOSSi ecosystem: from open-source EDA tools, to an open-source PDK, to open-source IP blocks and frameworks.

The SoC features the CV32E40X from the OpenHW Group as RISC-V core and provides basic peripherals. The eFPGA of Greyhound is generated by FABulous, an embedded FPGA framework. The eFPGA fabric consists of 784x LUT4+FF, 7x SRAM, 7x MAC, 14x register files and more. Greyhound's eFPGA can be used as a custom instruction extension for the RISC-V core, as a peripheral of the SoC or as a completely standalone FPGA with 32 I/Os. Custom tiles were created to enable warmboot functionality and allow communication with the SoC. Thanks to FABulous, the user bitstream for the FPGA can be generated using the upstream Yosys and nextpnr toolchain.

Greyhound was taped out in April 2025 through the IHP Free MPW runs, which are funded by a public German project FMD-QNC (16ME083).

==Software==
===General information===

* Repository: https://github.com/mole99/greyhound-ihp
* Greyhound has been taped out in April 2025 through the [https://ihp-open-ip.readthedocs.io/en/latest/ IHP Free MPW runs]