From the RISC-V spec to a low-tech SoC, passing by SpinalHDL, VexRiscv and OpenOCD
Revision as of 19:37, 2 March 2019 by Charles.papon (talk | contribs) (Created page with " * Speaker(s): Charles Papon * email: charles.papon.90@gmail.com ==Slides== Incomming ==Abstract== This talk will fly around the different aspects of a low-tech SoC, by expo...")
- Speaker(s): Charles Papon
- email: charles.papon.90@gmail.com
Slides
Incomming
Abstract
This talk will fly around the different aspects of a low-tech SoC, by exposing the practical case of VexRiscv and the related technologies.
General information
- Repository: https://github.com/SpinalHDL/VexRiscv
- Main documentation website: https://spinalhdl.github.io/SpinalDoc-RTD/