Difference between revisions of "From the RISC-V spec to a low-tech SoC, passing by SpinalHDL, VexRiscv and OpenOCD"
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(Created page with " * Speaker(s): Charles Papon * email: charles.papon.90@gmail.com ==Slides== Incomming ==Abstract== This talk will fly around the different aspects of a low-tech SoC, by expo...") |
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==Abstract== | ==Abstract== | ||
This talk will fly around | This talk will fly around different aspects of designing the netlist of a low-tech SoC, by exposing the practical case of VexRiscv the related technologies and challenges. | ||
===General information=== | ===General information=== | ||
* Repository: https://github.com/SpinalHDL/VexRiscv | * Repository: https://github.com/SpinalHDL/VexRiscv | ||
* Main documentation website: https://spinalhdl.github.io/SpinalDoc-RTD/ | * Main documentation website: https://spinalhdl.github.io/SpinalDoc-RTD/ | ||
===Roadmap=== | |||
* The project seeks help on: Exploring new hardware description methodologies |
Revision as of 11:35, 10 March 2019
- Speaker(s): Charles Papon
- email: charles.papon.90@gmail.com
Slides
Incomming
Abstract
This talk will fly around different aspects of designing the netlist of a low-tech SoC, by exposing the practical case of VexRiscv the related technologies and challenges.
General information
- Repository: https://github.com/SpinalHDL/VexRiscv
- Main documentation website: https://spinalhdl.github.io/SpinalDoc-RTD/
Roadmap
- The project seeks help on: Exploring new hardware description methodologies