From the RISC-V spec to a low-tech SoC, passing by SpinalHDL, VexRiscv and OpenOCD

• Speaker(s): Charles Papon
• email: charles.papon.90@gmail.com

Downloads

• Slides
• Video recording

Abstract

This talk will fly around different aspects of designing the netlist of a low-tech SoC, by exposing the practical case of VexRiscv the related technologies and challenges.

General information

• Repository: https://github.com/SpinalHDL/VexRiscv
• Main documentation website: https://spinalhdl.github.io/SpinalDoc-RTD/

Roadmap

• The project seeks help on: Exploring new hardware description methodologies