FSiC2026
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| Free Silicon Conference 2026 | |
|---|---|
 | |
| Genre | Free software and free hardware development conference |
| Location(s) | University of Ljubljana, Faculty of Electrical Engineering |
| Country | Slovenia |
| Website | wiki.f-si.org/index.php/FSiC2026 |
The 2026 Free Silicon Conference (FSiC) will take place at University of Ljubljana, Faculty of Electrical Engineering, on July 6 to 8 2026 (Monday to Wednesday). This event will build on previous FSiC editions. The conference will connect experts and enthusiasts who want to build a complete free and open-ource CAD ecosystem for designing analog and digital integrated circuits. The conference will cover the full spectrum of the design process, from system architecture to layout and verification.
Submission
This is your opportunity to present your project and to get in touch with the community. To propose a talk, please submit a title and a short summary at fsic2026 'at' f-si.org. Topics are not restricted to the tentative program.
Participation
To participate in the conference, both as speaker and as attendee, it is necessary to register here:
Registration to the conference
As in the 2025 edition, we have three types of tickets:
- for non-profit, enthusiasts, or free-time contributors: free admission
- for affiliated students and private individuals: early bird 160 €, regular 200 €
- for professionals: early bird 340 €, regular 400 €
Early bird discount ends on 30 April.
After completing the registration you will receive an official invoice from:
Free Silicon Foundation Sonneggstrasse 21 3123 Belp Switzerland VAT-ID: SI86289748
Tentative program
Digital design and logic-synthesis
- Noam Cohen (KeplerTech.io), Kepler-formal
- Andreas Krall (TU Wien), Progress of OpenVADL: tensors and hardware generation (lightning talk)
- Mattis Hasler (Barkhausen Institut), Choc/SiCo: unifying hardware testcases from unittests all the way to board-on-desk setups (lightning talk)
- Dirk Koch (Novel Computing Technologies Group, Heidelberg University), Towards All-Open Customizable and Reconfigurable SoCs
Ongoing FOS silicon projects
- Sylvain Munaut (smunaut), RV32 register file design on SKY130: a novice's approach
- Diarmuid Collins (Slice Semiconductor), Open source design of a programmable gain instrumentation amplifier, with industry comparable accuracy / noise and common mode rejection performance across full process / voltage (±5%) / temperature (-40 → 125degC)
- Alfonso Cortes (Inria), Design and implementation of a custom RISC-V system using Chipyard and LibreLane
- Martin Schoeberl (DTU Compute), First student tapeout at the Technical University of Denmark
- Torsten Mähne (Berner Fachhochschule), Low-Power Analog IC Design Using Open-source EDA Tools and PDK – A Low-Power Rail-to-Rail Operational Amplifier
- Jure Vreca (Jožef Stefan Institute - Computer Systems, Ljubljana), RVJ1: Designing an Open Source CPU and MCU using Open Source EDA
Foundries, PDKs and standard-cell libraries
- Rene Scholz (IHP Microelectronics), IHP openPDK and open-silicon MPW: pushing open-source EDA tools to productive chip design
- Leo Moser (wafer.space), Challenges of the first wafer.space shuttle run
- Mauricio Montanares (IHP Microelectronics), Open-source assembly design kit for heterogeneous chiplet integration
- Clyde Laforge (CERN), Towards a hassle-free GF180 KLayout flow (lightning talk)
- Jeremy Alcim (Logilib), logilib, portable parameterized digital library with multi-PDK dispatch (lightning talk)
- Emre Ozer (Pragmatic Semiconductor), FlexIC Meets Open-Source EDA: Enabling Rapid, Low-Cost Flexible Electronics
- Joaquin Matres (gdsfactory), Accelerating Chip Design with GDSFactory Programmatic IHP PDK
Analog flow, transistor modelling and circuit simulation
- Arpad Buermen (University of Ljubljana), VACASK: One year toward a modern open analog simulation stack
- Robert Taylor (ChipFlow), Analog, GPUs, and AI. Oh my!
- Pepijn de Vos (NyanCAD), NyanCAD, or there and back again
- Pepijn de Vos (NyanCAD), CedarSim is dead, long live CedarSim!
- David Lanzendörfer (LibreSilicon), Visual ReAct-agents designing analog VLSI-FOSSi layouts in LibrePDK (lightning talk)
- Žiga Rojec (University of Ljubljana), LLMEDA: human-in-the-loop LLM-enabled analog topology synthesis with PyOPUS
- Felix Salfelder (Gnucap), Verilog-AMS in Gnucap (lightning talk)
- Simon Dorrer (Johannes Kepler University (JKU) Linz), From idea to tapeout: an open-source analog mixed-signal design flow with the IHP Open-PDK
- Kennedy Caisley (University of Bonn), Programmatic analog IC design (without reinventing the wheel)
- Dietmar Warning (IHP Microelectronics), NGSPICE - status update and recent developments with OpenPDK support
- Krzysztof Herman (IHP Microelectronics), Felix Salfelder (Gnucap) and Lukas Deutz, Verilog-AMS support in the IHP Open PDK using the Gnucap simulator
- Lukas Deutz, Compile-time parameter binding: is it worth it? (lightning talk)
- Patrick Fath (Johannes Kepler University (JKU) Linz), Towards a practical open-source RF-SoC design flow: lessons from a 40-GHz tapeout in IHP SG13G2
- Sumanto Kar (FOSSEE, IIT Bombay), IHP Open PDK SG13G2 Integration in eSim for Advanced IC Design and Simulation
- Tobias Kaiser (TU Berlin), ORDeC: Progress in text-driven analog IC design from schematic to layout
- Philippe Sauter (ETH Zürich), Reusable Logic Pre-Optimization for Better Open-Source Arithmetic QoR
- Pascal Febvre and Arsenii Serebriakov (FrugalEDA), FrugalEDA, an open-source software suite to design superconducting quantum circuits
- Santiago Hofwimmer (Johannes Kepler University (JKU) Linz), Chipify: A High-Performance PVT & Mismatch Simulation Wrapper (lightning talk)
Hardware security
- Sebastian Haas (Barkhausen Institute), M³ secure tape-out platform (lightning talk)
- Thorben Moos (UCLouvain), The Cloneless series of open-source ASICs for physical security evaluation
Economic sustainability and hardware licences
- Javier Serrano (CERN), The CERN Open Hardware Licence for IC and FPGA designs
Policy, EU projects and funding opportunities
- Tina Tauchnitz (VDI/VDE-IT), From initiative to impact: expanding Germany's chip design capabilities
Back-end design tools
- Yibo Lin (Peking University), DREAMPlace
- Daniel Schultz (aesc), BlenderGDS (lightning talk)
- Daniel Schultz (aesc), gdsfill (lightning talk)
- Ole Richter (DTU), A more modern way to design (open source) (memory) macro compilers
- Hagen Sankowski (LibreSilicon), WYSIWYG - "What you see is what you get?" - "Hopefully!" (lightning talk)
- David Kellerer-Pirklbauer (Johannes Kepler University (JKU) Linz), A fully-programmatic layout generation & verification flow for IHP-Open PDK PCells and RF-structures utilizing GDSFactory & Palace
- Mehta Stavan Dhaval (IIT Bombay), SAM-Route: a cornerstitch-based multi-layer router for ACT-generated custom cells
- Max Martin Paulenz (TU Dresden), OpenOrchestrator: schematic-driven layout with open-source EDA tools (lightning talk)
- Hao Wang (Institute of Computing Technology, Chinese Academy of Sciences), ECOS Studio: an RTL-to-chip silicon design solution with open-source EDA, IP, and PDK
- Jack Luar (Precision Innovations), OpenROAD Model Context Protocol (MCP) (lightning talk)
- Mohamed Gaber & Leo Moser (LibreLane), LibreLane 3.0 and Plugin Flows
- Andrew Kahng (UC San Diego), Coding agents to accelerate open-source EDA innovation
- Martin Köhler (martinjankoehler), KLayout Productivity Suite – Boosting Efficiency in Manual IC Layout Design
- Tamas Hubai (microlane), microlane – Writing a minimal RTL to GDS flow from scratch
Teaching and education
- "One Student One Chip" initiative (Institute of Computing Technology, Chinese Academy of Sciences), "One Student One Chip" initiative: learn to build RISC-V chips from scratch with MOOC
- Friedrich Beckmann (TH Augsburg), OpenROAD, SpinalHDL and friends in VLSI courses at UAS Augsburg
Standards
Practical information
The conference takes place at the Faculty of Electrical Engineering in
Tržaška cesta 25 SI-1000 Ljubljana Slovenia
The main entrance faces Tržaška cesta. During breaks, participants are welcome to use the canteen (with garden) or the nearby park.
For venue tips see here.
Organizing committee
Lead organizers (overall coordination and local host)
‟Technology is political. I stand for defending free access to technology and the right for transparency.”
‟Open-source EDA transforms chip design from a gate-kept industry into an accessible skill for all.”
‟I like to understand technology, to adapt and enhance it. Technology should not be mythical or owned by experts only, it needs to be comprehensible.”
Programme co-organizers
‟For democracy to thrive, technology must empower, not control.”
‟I am passionate about helping people with my technical skills. Coding EDA is like gardening to me: may it grow and feed people.”
‟Open-source tools and technology gives freedom to students to explore chip design on their own and on their computers, not limiting them to the walled garden of a dedicated lab at the University.”
‟Our goal is to make open source EDA tools and design flows easily accessible and usable for anyone who wants to get into ASIC chip design, test new design ideas and develop them to a manufacturable level.”
Donations and sponsorships
We are looking for sponsors to cover extra services at the conference. Organizations wishing to gain visibility at the venue may also reserve a dedicated exhibition table and/or a poster wall. In case of interest, please contact us at fsic2026'at'f-si.org.
Acknowledgements
This conference is co-funded by the Swiss State Secretariat for Education, Research and Innovation (SERI) under the NGI0 Commons Fund project. The NGI0 Commons Fund has received funding from the European Union’s Horizon Europe research and innovation programme under grant agreement No. 101135429.
