Difference between revisions of "FSiC2022"

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| name = Notice
| name = Notice
| demospace = {{{demospace|}}}
| demospace = {{{demospace|}}}
| text = '''The preliminary conference schedule is now online.'''  
| text = '''Most video recordings are now online on [https://peertube.f-si.org Peertube].'''  
}}  
}}  
{{Infobox recurring event
{{Infobox recurring event
|name              = Free Silicon Conference 2022
|name              = Free Silicon Conference 2022
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== News ==
== News ==
The conference is over! We are now collecting and publishing the missing material. The video recordings are being edited and will be updated on [https://peertube.f-si.org Peertube] in the coming days.
From '''April 15''' we continue with direct invitations and we work to consolidate the program.
From '''April 15''' we continue with direct invitations and we work to consolidate the program.


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==== Keynote speech ====
==== Keynote speech ====
* 10:00-10:30, Jan Suhr ([https://www.nitrokey.com/ Nitrokey]), ''title to be announced''
* 10:00-10:30, Jan Suhr ([https://www.nitrokey.com/ Nitrokey]), ''[https://peertube.f-si.org/videos/watch/51218911-1bbc-4354-b6e4-1eb7c170686f Open Source Has Won. Why Open Hardware, Silicon Will Win Next]''


==== High-level design ====
==== High-level design ====
* 10:30-11:00, Charles Papon ([https://github.com/SpinalHDL SpinalHDL]), ''Composing an out-of-order CPU using software technics''
* 10:30-11:00, Charles Papon ([https://github.com/SpinalHDL SpinalHDL]), ''[[Composing an out-of-order CPU using software technics]]''
* 11:00-11:30, Christoph Grimm ([https://cps.cs.uni-kl.de/en/staff/christoph-grimm-prof-dr/ Kaiserslautern University]), ''Inclusive Modeling with SysMD''
* 11:00-11:30, Christoph Grimm ([https://cps.cs.uni-kl.de/en/staff/christoph-grimm-prof-dr/ Kaiserslautern University]), ''[[Inclusive Modeling with SysMD]]''
* 11:30-12:00 Tristan Gingold ([http://ghdl.free.fr/ GHDL]), Wishbone: a free SoC bus family
* 11:30-12:00 Tristan Gingold ([http://ghdl.free.fr/ GHDL]), ''[[Wishbone: a free SoC bus family]]''
* '''12:00-13:30''', '''lunch''' break  
* '''12:00-13:30''', '''lunch''' break  
* 13:30-14:00, Johan Euphrosine (Google), ''Porting software to hardware using XLS and open source PDKs''
* 13:30-14:00, Johan Euphrosine (Google), ''[[Porting software to hardware using XLS and open source PDKs]]''
* 14:00-14:30, Tristan Gingold ([http://ghdl.free.fr/ GHDL]), ''Synthesis with ghdl''
* 14:00-14:30, Tristan Gingold ([http://ghdl.free.fr/ GHDL]), ''[[Synthesis with ghdl]]''


==== Hardware security ====
==== Hardware security ====
* 14:30-15:00, Tomas Aidukas ([https://www.psi.ch/en/people/tomas-aidukas Paul Scherrer Institut]), ''3D X-ray Nano Imaging for Chip Inspection''
* 14:30-15:00, Tomas Aidukas ([https://www.psi.ch/en/people/tomas-aidukas Paul Scherrer Institut]), ''[[3D X-ray Nano Imaging for Chip Inspection]]''
* 15:00-15:30, Roselyne Chotin ([https://www.lip6.fr/actualite/personnes-fiche.php?ident=P206 Sorbonne Université - LIP6]) and Lilia Zaourar ([https://list.cea.fr/fr/ CEA]), ''Logic locking as an example to introduce security in an open CAD flow''
* 15:00-15:30, Roselyne Chotin ([https://www.lip6.fr/actualite/personnes-fiche.php?ident=P206 Sorbonne Université - LIP6]) and Lilia Zaourar ([https://list.cea.fr/fr/ CEA]), ''[https://peertube.f-si.org/videos/watch/499d7659-76fa-452e-9f99-1f40caa1a317 Logic locking as an example to introduce security in an open CAD flow]''


==== On-going FOS silicon projects ====
==== On-going FOS silicon projects ====
* 15:30-16:00, Matthew Venn, ''How many designs can you fit on a single die''<br><br>
* 15:30-16:00, Matthew Venn ([https://www.yosyshq.com/ YosysHQ], [https://www.chipflow.io/ ChipFlow]), ''[[How many designs can you fit on a single die]]''<br><br>
* '''16:00-16:30''', '''Afternoon break.''' Coffee is served on-campus<br><br>
* '''16:00-16:30''', '''Afternoon break.''' Coffee is served on-campus<br><br>
* 16:30-17:00, Hagen Sankowski, ''Standard Cell Library report''
* 16:30-17:00, Hagen Sankowski ([https://libresilicon.com/ Libre Silicon]), ''[[Standard Cell Library report]]''
* 17:00-17:30, Sebastian Wiedemann, ''go2async: A high-level synthesis tool for asynchronous circuits''
* 17:00-17:30, Sebastian Wiedemann ([https://www.tuwien.at/ TU Wien]), ''[[go2async: A high-level synthesis tool for asynchronous circuits]]''
* 17:30-18:00, Matthias Koefferlein, KLayout XSection tool - Deep insights or nonsense in colors?
* 17:30-18:00, Matthias Koefferlein ([https://klayout.de KLayout]), ''[[KLayout XSection tool - Deep insights or nonsense in colors?]]''


==== Evening program ====
==== Evening program ====
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====Keynote speech====
====Keynote speech====
* 9:30-10:00, Frank Karlitschek ([https://nextcloud.com/team/ Nextcloud]), ''Why Open Hardware and Open Software are necessary for our future''
* 9:30-10:00, Frank Karlitschek ([https://nextcloud.com/team/ Nextcloud]), ''[https://peertube.f-si.org/videos/watch/89a2e2d7-537f-443e-8996-eae6daace5c6 Why Open Hardware and Open Software are necessary for our future]''


====Foundries and PDKs====
====Foundries and PDKs====
* 10:00-10:30, Frank Vater ([https://www.ihp-microelectronics.com/services/research-and-prototyping-service/fast-design-enablement IHP Microelectronics]), ''OpenSource PDK - A key enabler to unlock the potential of an open source design flow''
* 10:00-10:30, Frank Vater ([https://www.ihp-microelectronics.com/services/research-and-prototyping-service/fast-design-enablement IHP Microelectronics]), ''[[OpenSource PDK - A key enabler to unlock the potential of an open source design flow]]''
* 10:30-11:00, Kholdoun Torki ([https://mycmp.fr/ CMP]), ''65nm CMOS Design-Flows on Free and Open-Source Tools : An Overview''
* 10:30-11:00, Kholdoun Torki ([https://mycmp.fr/ CMP]), ''[[65nm CMOS Design-Flows on Free and Open-Source Tools : An Overview]]''
* 11:00-11:30, Staf Verhaegen ([https://www.chips4makers.io/blog Chip4Makers]), ''PDKMaster & co.: a framework for scalable and technology portable standard cell, IO and SRAM libraries''
* 11:00-11:30, Staf Verhaegen ([https://www.chips4makers.io/blog Chip4Makers], [https://chipflow.io ChipFlow]), ''[[PDKMaster & co.: a framework for scalable and technology portable standard cell, IO and SRAM libraries]]''
* 11:30-12:00, Naohiko Shimizu ([http://labo.nshimizu.com/ Tokai University]), ''Challenge to Fabricate LSI without NDA with Open Method''
* 11:30-12:00, Naohiko Shimizu ([http://labo.nshimizu.com/ Tokai University]), ''[[Challenge to Fabricate LSI without NDA with Open Method]]''
* '''12:00-13:30''', '''lunch''' break  
* '''12:00-13:30''', '''lunch''' break


====Schematic editors====
====Schematic editors====
* 13:30-14:00, Stef Schippers ([https://github.com/StefanSchippers/xschem XSCHEM]), ''XSCHEM - circuit schematic editor for VLSI, ASIC, PCB design''
* 13:30-14:00 (not present), Stef Schippers ([https://github.com/StefanSchippers/xschem XSCHEM]), ''[[XSCHEM - circuit schematic editor for VLSI, ASIC, PCB design]]''
* 14:00-14:30, Elen Eisendle ([https://gitlab.com/edea-dev EDeA]), ''title to be announced''
 
====Tutorial====
* 13:30-14:00, Kholdoun Torki ([https://mycmp.fr/ CMP]), [https://peertube.f-si.org/videos/watch/65b509f5-6040-43c6-aac1-78cb7eded5a4 Design flow tutorial]
 
====Microcontrollers====
* 14:00-14:30, Philipp Klaus Krause ([https://uni-freiburg.de/ Uni Freiburg]), ''[[f8|f8 - an architecture for 8-bit µC based on lessons learned from the free Small Device C Compiler]]''


====Photonics====
====Photonics====
* 14:30-15:00, Ronald Broeke ([https://nazca-design.org/about/ Nazca Design]), ''Nazca Design, a balancing act between open source tooling and propriety PDKs in photonics''
* 14:30-15:00, Ronald Broeke ([https://nazca-design.org/about/ Nazca Design]), ''[https://peertube.f-si.org/videos/watch/bbabcee3-a7ba-4116-905a-139e9f10d5d8 Nazca Design, a balancing act between open source tooling and propriety PDKs in photonics]''
* 15:00-15:30, Joaquin Matres Abril (Google), ''gdsfactory''
* 15:00-15:30, Joaquin Matres Abril (Google), ''[[gdsfactory]]''
* 16:00-16:30, Dima Pustakhod ([https://research.tue.nl/en/persons/dzmitry-pustakhod TU/e]), ''title to be announced''<br><br>
* 15:30-16:00, Dima Pustakhod ([https://research.tue.nl/en/persons/dzmitry-pustakhod TU/e]), ''[[openEPDA: photonic PDKs with open standards]]''<br><br>
* '''16:00-17:00''', '''Afternoon break.''' Coffee is served on-campus<br><br>
* '''16:00-17:00''', '''Afternoon break.''' Coffee is served on-campus<br><br>


====Mixed-signal/analog design and transistor modelling====
====Mixed-signal/analog design====
* 17:00-17:30, Felix Salfelder ([https://savannah.gnu.org/git/?group=gnucap GnuCap]), ''title to be announced''
* 17:00-17:30, Felix Salfelder ([https://savannah.gnu.org/git/?group=gnucap GnuCap]), ''[[Merging Gnucap and Qucs -- The Why and How]]''
 
* 17:30-18:00, Tim Edwards ([http://opencircuitdesign.com/ Open Circuit Design]), ''[[Whom do you trust?: Validating process parameters for open-source tools]]''
====Parasitic extraction====
* 17:30-18:00, Tim Edwards ([http://opencircuitdesign.com/ Open Circuit Design]), ''Whom do you trust?: Validating process parameters for open-source tools''


==== Evening program ====
==== Evening program ====
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==== Back-end flow: placement, routing, timing closure ====
==== Back-end flow: placement, routing, timing closure ====
* 9:30-10:00, Thomas Kramer ([https://libreda.org/ LibrEDA]), ''[[LibrEDA - digital place-and-route framework from scratch]]''
* 9:30-10:00, Thomas Kramer ([https://libreda.org/ LibrEDA]), ''[[LibrEDA - digital place-and-route framework from scratch]]''
* 10:00-10:30, Gabriel Gouvine, ''Digital placement algorithms in [http://coriolis.lip6.fr/ Coriolis]''
* 10:00-10:30, Gabriel Gouvine ([http://coriolis.lip6.fr/ Coriolis]), ''[[Digital placement algorithms in Coriolis]]''
* 10:30-11:00, Christophe Alexandre ([https://github.com/xtofalex/naja Naja]), ''[[Naja: an open source framework for EDA post synthesis flow development]]''


==== Tutorials ====
==== Tutorials ====
* 10:30-12:00, Matthias Koefferlein ([https://klayout.de/ KLayout]), ''Tutorial and FAQ on physical verification, DRC+LVS''
* 11:00-12:00, Matthias Koefferlein ([https://klayout.de/ KLayout]), ''[[Tutorial and FAQ on physical verification, DRC+LVS]]''
* '''12:00-13:30''', '''lunch''' break
* '''12:00-13:30''', '''lunch''' break
==== Funding opportunities ====
* 13:30-13:45, Michiel Leenaars ([https://nlnet.nl/ NLnet Foundation]), ''[https://nlnet.nl/assure NGI Assure] and [https://nlnet.nl/entrust NGI0 Entrust] grant programmes''


==== Paving the road for open source flow: gaps, challenges, opportunities ====
==== Paving the road for open source flow: gaps, challenges, opportunities ====
* 13:30-15:00, ''open discussion''
* 13:45-15:30, ''open discussion''
 
* 15:30-16:00, conclusions
==== Industry session ====
* 15:00-16:00, industry representatives
* 16:00-16:30, conclusions


== Practical information ==
== Practical information ==
Coffees are kindly offered by Sorbonne Université, LIP6, IRILL and CNRS. '''Lunches are self organized by the attendees.'''
*[[FSiC2022 venue|Venue, map, hotels]]
*[[FSiC2022 venue|Venue, map, hotels]]
*[[Guidelines for invited speakers]]
*[[Guidelines for invited speakers]]
Line 194: Line 200:


==Academic Sponsors==
==Academic Sponsors==
[[File:SUS_LIP6_CNRSnew.jpg|500px]]
[[File:SUS_LIP6_CNRSnew.jpg|500px|link=https://www.lip6.fr]]
[[File:irill.png|300px]]
[[File:irill.png|300px|link=https://www.irill.org]]

Latest revision as of 13:25, 11 August 2022

Free Silicon Conference 2022
Fsic2022 logo.png
GenreFree software and free hardware development conference
Location(s)Paris, Sorbonne Université
CountryFrance
Websitewiki.f-si.org/index.php/FSiC2022


The 2022 Free Silicon Conference (FSiC) will take place in Paris (Sorbonne) on July 7,8,9 2022 (Thursday to Saturday). This event will build on top of the 2019 edition. The conference will connect experts and enthusiasts who want to build a complete Free and Open Source CAD ecosystem for designing analog and digital integrated circuits. The conference will cover the full spectrum of the design process, from system architecture, to layout and verification. The conference consists of three full days, including a Saturday for facilitating those who are involved as non-professionals. After the daily talks, the discussion will continue until late in an informal and relaxed atmosphere at the nearby botanical garden "Jardin des plantes", at the ancient roman theater "Arènes de Lutèce" or (depending on the weather) in the on-campus facilities.

Objectives and motto

The goal of FSiC is to make the technology accessible to small businesses, startups, universities and schools. Students, makers and professional should have direct access to education, without barriers, paywalls and legal burdens.

What's the value of multi-billion public investments if there aren't designers, engineers and other experts who can operate the industry and who master the tools to innovate?

We all took apart watches and radios when we were kids, hence we learned how they work. It is time to look inside chips and their tool-chains so that we can study, improve and trust them.

The conference motto is therefore: Education, dissemination and innovation by openness and collaboration!

News

The conference is over! We are now collecting and publishing the missing material. The video recordings are being edited and will be updated on Peertube in the coming days.

From April 15 we continue with direct invitations and we work to consolidate the program.

Until April 15 we are calling for talks. During this period the conference program will still be fluid: new sessions may appear and new topics may be added. For example, we are considering adding a session about public funding opportunities and one about FOS business models. If you want to propose a talk please contact us by writing at fsic2022 'at' f-si.org.

During the month of February we run the "search and discovery" phase: We asked our network (through email and mastodon) to propagate the FSiC announcement and to suggest us new potentials speakers/attendees. We were suggested ten new names. Thanks for the contributions!

Abstract submission

For submitting an abstract or a title, or just for proposing informally a talk, contact us per email at fsic2022 'at' f-si.org. Do not hesitate!

Participation

Participation to the conference is free of charge but the attendance must be reserved per email at fsic2022 'at' f-si.org. Details will be announced on this page and over the mastodon channel.

Organizing committee

Fsic2022 mml.png
Marie-Minerve Louerat
Scientist and Teacher
‟I have a passion for educating and teaching students, to give them tools for life and learning.”
Fsic2022 la.png
Luca Alloatti
Libre Hardware Promoter
‟Technology is political. I stand for defending free access to technology and the right for transparency.”
Fsic2022 tk.png
Thomas Kramer
Skeptical Technology Enthusiast
‟I like to understand technology, to adapt and enhance it. Technology should not be mythical or owned by experts only, it needs to be comprehensible.”
Fsic2022 mk.png
Matthias Köfferlein
FOSS EDA Author
‟I am passionate about helping people with my technical skills. Coding EDA is like gardening to me: may it grow and feed people.”

Conference program

July 7, Thursday (Day 1)

  • 9:00-9:30, Registration and coffee

Welcome

  • 9:30-9:45, Welcome from the LIP6
  • 9:45-9:55, Welcome from the Free Silicon Foundation

Keynote speech

High-level design

Hardware security

On-going FOS silicon projects

Evening program

  • 18:00-20:00, Gathering at the Jardin des plantes

July 8, Friday (Day 2)

  • 8:30-9:30, Early bird coffee and tea

Keynote speech

Foundries and PDKs

Schematic editors

Tutorial

Microcontrollers

Photonics

Mixed-signal/analog design

Evening program

July 9, Saturday (Day 3)

  • 8:30-9:30, Early bird coffee and tea

Back-end flow: placement, routing, timing closure

Tutorials

Funding opportunities

Paving the road for open source flow: gaps, challenges, opportunities

  • 13:45-15:30, open discussion
  • 15:30-16:00, conclusions

Practical information

Coffees are kindly offered by Sorbonne Université, LIP6, IRILL and CNRS. Lunches are self organized by the attendees.

Donations

We are looking for sponsors to cover the conference costs. In case of interest, please write at fsic2022 'at' f-si.org. Bank coordinates are available here.

Sponsors

Miromico.svg RedCatDevices.jpg Nitrokey.svg

Academic Sponsors

SUS LIP6 CNRSnew.jpg Irill.png