FSiC2019

The second Free Silicon Conference (FSiC) will be held at Sorbonne University (Paris) on March 14-16 2019. The conference will bring together experts and enthusiasts who want to build a complete Free and Open Source CAD ecosystem for designing analog and digital integrated circuits. The conference will cover the full spectrum of the design process, from system architecture, to layout and verification. The conference consists of three full days, including a Saturday for facilitating those who are involved as non-professionals. After the daily talks, the discussion will continue until late in an informal and relaxed atmosphere.

Abstract submission

Everybody is welcome to propose a talk by writing to fsic2019 'at' f-si.org. The submission window opened on December 12 2018 and will close on January 31 2019. Acceptance will be communicated by February 10.

Participation

Attending the conference is free of charge. However, due to the limited number of spaces available, places must be reserved before February 15 by writing at fsic2019 'at' f-si.org.

Organizing committee

• Marie-Minerve Louërat, lip6, CNRS
• Roselyne Chotin-Avot, lip6, Sorbonne University
• Jean-Paul Chaput, lip6, Sorbonne University
• Luca Alloatti, ETH-Zurich
• Matthias Koefferlein, KLayout project
• Sean Cross, Kosagi

Confirmed invited talks

The speakers below have confirmed their attendance. Speakers who gave a tentative agreement are not yet included.

Day 1

• Todd Weaver, Title to be announced, Purism
• echopen, The open-source and low-cost echo-stethoscope project
• Hernando Barragán, Wiring and visions, Wiring
• Philippe Coussy, GAUT, Lab-STICC Université Bretagne Sud
• Tristan Gingold, Title to be announced,GHDL
• Frédéric Pétrot, High level synthesis, Université Grenoble Alpes and TIMA Laboratory
• Pirouz Bazargan Sabet, Functional abstraction, Sorbonne Université and LIP6 Laboratory,
• Charles Papon, From the RISC-V spec to a low-tech SoC, passing by SpinalHDL, VexRiscv and OpenOCD, SpinalHDL
• Jean Bruant, State of the art on high-level hardware description languages to generate VHDL or SystemVerilog
• Telecom ParisTech, Simulation and formal verification at system level, TTool
• Holger Vogt, Title to be announced, ngspice - open source spice simulator
• Wladek Grabinski, MOS-AK FOSS TCAD/EDA Perspective, MOS-AK (EU)

Day 2

• Jean-Christophe Crébier, CMP add on services, CMP
• Speaker to be announced, FreePDK, FreePDK
• Speaker to be announced, LibreSilicon, LibreSilicon
• Thomas Benz, Converting 45nm transistor netlists to open standards, ETH Zurich
• Naohiko Shimizu, The development of the NSXLIB standard cell scalable library, Tokai University
• Thomas Kramer, FOS standard cell generator from scratch, ETH Zurich
• Liliana Andrade, Mixed-signal system modelling and simulation, Université Grenoble Alpes and TIMA Laboratory
• Gabriel Gouvine, Title to be announced, Local Solver
• Enrico Di Lorenzo, Parasitic extraction, FastFieldSolvers
• Tim Edwards, Title to be announced, Open Circuit Design, Qflow

Day 3

• Speaker to be announced, High level system modelling, hands-on computer session, GreenSocs
• Jean-Paul Chaput, The Alliance/Coriolis design flow, LIP6

Preliminary Program

March 14, Thursday (Day 1)

Introduction

• Motivations for Free and Open Source (FOS) hardware
• Impact on society, academia, makers, industry
• Impact on cybersecurity
• Politics and marketing
• Business opportunities

High-level system requirements

• Case studies from the perspective successful Open Hardware projects

High-level digital design (architectural and pre-layout)

• Architectural opportunities for FOS Hardware
• High-level hardware description languages to generate VHDL or SystemVerilog
• Formal verification
• High-level virtual prototyping

Analog design and simulation

• Comparison of FOS tools: Coriolis, qucs, KiCad.
• Ngspice
• SystemC-AMS

March 15, Friday (Day 2)

Foundries

• FOS hardware from the foundry's perspective: legal challenges and opportunities
• MakeLSI

Setting up the ingredients

• Importing PDKs into FOS formats
• Standard cell: generators and modelling
• Parametrized analog devices and topologies
• Parametrized Optical devices
• Memory generators

CAD internals and algorithms - how the tools work

• The role of databases
• Place algorithms
• Routing algorithms, global and detailed
• Timing analysis
• Power analysis
• Formal VHDL verification

Legal issues

• The constrains of typical NDAs
• Hardware FOS licenses. State-of-the-art

March 16, Saturday (Day 3)

CAD tool usage - demos

• Synthesis
• Place and route tools
• Timing analysis
• Clock distribution

Post place-and-route (P&R) verification and simulators

• Design Rule Check
• LVS
• Static Timing Analysis
• Fault modelling and Automatic Test Pattern Generators (ATPG)

Workshop

Further topics and questions raised during the conference will be discussed in plenary or in individual working groups.