Difference between revisions of "FSiC2019"

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==== Introduction and motivation for Free and Open Source (FOS) silicon ====
==== Introduction and motivation for Free and Open Source (FOS) silicon ====
* 10:00-10:30, [https://puri.sm/about/team/ Todd Weaver], ''[[The Future of Computing and Why You Should Care]]'', [https://puri.sm Purism]
* 10:00-10:30, [https://puri.sm/about/team/ Todd Weaver], ''[https://peertube.f-si.org/videos/watch/d8dcaf9e-88c7-44cf-9f97-d7d96d1d9b28 The Future of Computing and Why You Should Care]'', [https://puri.sm Purism]
* 10:30-11:00, [https://www.cs.hs-rm.de/~reith/ Steffen Reith], ''[[Towards digital sovereignty by open source (hardware)]]'', [https://www.hs-rm.de/ Hochschule RheinMain]
* 10:30-11:00, [https://www.cs.hs-rm.de/~reith/ Steffen Reith], ''[[Towards digital sovereignty by open source (hardware)]]'', [https://www.hs-rm.de/ Hochschule RheinMain]


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* 13:30-14:00, Daniela Genius, ''[[Model-Driven Performance Evaluation and Formal Verification for Multi-level Embedded System Design ]]'', [https://www.lip6.fr/actualite/personnes-fiche.php?ident=P96 Sorbonne Université, LIP6]
* 13:30-14:00, Daniela Genius, ''[[Model-Driven Performance Evaluation and Formal Verification for Multi-level Embedded System Design ]]'', [https://www.lip6.fr/actualite/personnes-fiche.php?ident=P96 Sorbonne Université, LIP6]
* 14:00-14:30, Charles Papon, ''[[From the RISC-V spec to a low-tech SoC, passing by SpinalHDL, VexRiscv and OpenOCD]]'', [https://github.com/SpinalHDL SpinalHDL]
* 14:00-14:30, Charles Papon, ''[[From the RISC-V spec to a low-tech SoC, passing by SpinalHDL, VexRiscv and OpenOCD]]'', [https://github.com/SpinalHDL SpinalHDL]
* 14:30-15:00, Jean Bruant, ''[[State of the art on high-level hardware description languages to generate VHDL or SystemVerilog]]'', [https://www.ovh.com/fr/ OVH] and [http://tima.imag.fr/sls/ TIMA Laboratory]
* 14:30-15:00, Jean Bruant, ''[https://peertube.f-si.org/videos/watch/d36f3f63-fad0-4334-b7b9-82f4be9c89ef State of the art on high-level hardware description languages to generate VHDL or SystemVerilog]'', [https://www.ovh.com/fr/ OVH] and [http://tima.imag.fr/sls/ TIMA Laboratory]
* 15:00-15:30, Florent Kermarrec, ''[https://docs.google.com/presentation/d/1KVgzcvEeqLPxYd4PO6zqF0mrlQBP86Vf6CQSiVO81I8/edit?usp=sharing LiteX: an open-source SoC builder and library based on Migen Python DSL]'', [http://enjoy-digital.fr/ Enjoy Digital]
* 15:00-15:30, Florent Kermarrec, ''[[LiteX: an open-source SoC builder and library based on Migen Python DSL]]'', [http://enjoy-digital.fr/ Enjoy Digital]


====Mixed-signal/analog design and transistor modelling====
====Mixed-signal/analog design and transistor modelling====
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* 12:00-12:30, Naohiko Shimizu, ''[[The development of the NSXLIB standard cell scalable library]]'', [http://labo.nshimizu.com/ Tokai University]<br><br>
* 12:00-12:30, Naohiko Shimizu, ''[[The development of the NSXLIB standard cell scalable library]]'', [http://labo.nshimizu.com/ Tokai University]<br><br>
* '''12:30-13:30''', '''lunch''' is served at the on-campus [http://www.locations.espaces.upmc.fr/fr/presentation_espaces/campus_jussieu/patio.html Le Patio]<br><br>
* '''12:30-13:30''', '''lunch''' is served at the on-campus [http://www.locations.espaces.upmc.fr/fr/presentation_espaces/campus_jussieu/patio.html Le Patio]<br><br>
* 13:30-14:00, Hagen Sankowski, ''[[Popcorn - or how many cells your Standard Cell Library has?]]'', [http://libresilicon.com/ LibreSilicon]
* 13:30-14:00, Hagen Sankowski, ''[https://peertube.f-si.org/videos/watch/2bcbad29-2d87-4d1f-b193-ff9317dbc439 Popcorn - or how many cells your Standard Cell Library has?]'', [http://libresilicon.com/ LibreSilicon]
* 14:00-14:30, [https://www.soe.ucsc.edu/people/mrg Matthew Guthaus], ''[[OpenRAM: An Open-Source Memory Compiler]]'', [https://vlsida.github.io/OpenRAM/ OpenRAM], UCSC
* 14:00-14:30, [https://www.soe.ucsc.edu/people/mrg Matthew Guthaus], ''[[OpenRAM: An Open-Source Memory Compiler]]'', [https://vlsida.github.io/OpenRAM/ OpenRAM], UCSC
* 14:30-15:00, Thomas Kramer, ''[[FOS standard cell generator from scratch]]'', [https://www.ethz.ch ETH Zurich]
* 14:30-15:00, Thomas Kramer, ''[[FOS standard cell generator from scratch]]'', [https://www.ethz.ch ETH Zurich]
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* 17:00-17:30, Enrico Di Lorenzo, [[Open_Source_Parasitic_Extraction|''Open Source parasitic extraction - solutions, challenges, and business models'']], [http://www.fastfieldsolvers.com FastFieldSolvers]
* 17:00-17:30, Enrico Di Lorenzo, [[Open_Source_Parasitic_Extraction|''Open Source parasitic extraction - solutions, challenges, and business models'']], [http://www.fastfieldsolvers.com FastFieldSolvers]
* 17:30-18:00, Tim Edwards, ''[[The Raven chip: First-time silicon success with qflow and efabless]]'', [http://opencircuitdesign.com/ Open Circuit Design, Qflow]
* 17:30-18:00, Tim Edwards, ''[[The Raven chip: First-time silicon success with qflow and efabless]]'', [http://opencircuitdesign.com/ Open Circuit Design, Qflow]
* 18:00-18:30, Hagen Sankowski, ''[[Somebody is using the Advanced Library Format (ALF)? We like to do!]]'', [http://libresilicon.com/ LibreSilicon]
* 18:00-18:30, Hagen Sankowski, ''[https://peertube.f-si.org/videos/watch/6b322173-010b-425e-a98f-dde0b628c989 Somebody is using the Advanced Library Format (ALF)? We like to do!]'', [http://libresilicon.com/ LibreSilicon]


====Evening program "beer & baguette" at the on-campus Tour Zamansky, 24th floor (room with a view)====
====Evening program "beer & baguette" at the on-campus Tour Zamansky, 24th floor (room with a view)====

Revision as of 17:00, 16 July 2019

Free Silicon Conference 2019
Fsic2019 logo.svg
GenreFree software and free hardware development conference
Location(s)Paris, Sorbonne Université
CountryFrance
Websitewiki.f-si.org/index.php/FSiC2019

The second Free Silicon Conference (FSiC) took place at Sorbonne Université (Paris) on March 14-16 2019. The conference brought together experts and enthusiasts who want to build a complete Free and Open Source CAD ecosystem for designing analog and digital integrated circuits. The conference covered the full spectrum of the design process, from system architecture, to layout and verification. The conference consisted of three full days, including a Saturday for facilitating those who are involved as non-professionals. After the daily talks, the discussion continued until late in an informal and relaxed atmosphere at the on-campus caves Esclangon.

All video recordings are available on peertube.

Video recordings, slides and documentation

All the talks have been recorded and can be watched on peertube. Extra documentation and the slides of most talks can be found by clicking on the respective titles in the program below.

Participation

Attendance to the conference was free of charge. Lunches, dinners and drinks were offered. However, due to the limited number of spaces available, seats had to be reserved before February *21* by writing at fsic2019 'at' f-si.org.

The submission window closed on January 31 2019.

Organizing committee

  • Marie-Minerve Louërat, LIP6, CNRS
  • Roselyne Chotin, LIP6, Sorbonne Université
  • Jean-Paul Chaput, LIP6, Sorbonne Université
  • Luca Alloatti, ETH-Zurich
  • Matthias Koefferlein, KLayout project
  • Sean Cross, Kosagi
  • Thomas Kramer, ETH-Zurich

Conference program

March 14, Thursday (Day 1)

Registration

  • 9:00-9:30, Registration and coffee

Welcome

Introduction and motivation for Free and Open Source (FOS) silicon

High-level digital design (session I)

Mixed-signal/analog design and transistor modelling

Evening program "beer & baguette" on-campus

  • 19:00-22:00: drinks are served
  • 19:30: dinner is served
  • 21:00: end of the day

March 15, Friday (Day 2)

Morning Coffee

  • 8:30-9:00, Early bird coffee and tea

Impact of FOS hardware

Foundries, PDKs and cell libraries

Back-end flow and algorithms

Evening program "beer & baguette" at the on-campus Tour Zamansky, 24th floor (room with a view)

  • 18:30-21:00: drinks are served
  • 19:30: dinner is served
  • 21:00: end of the day

March 16, Saturday (Day 3)

Morning Coffee

  • 8:30-9:00, Early bird coffee and tea

Licenses

High-level digital design (session II)

Analog back-end design

Back-end design

Practical information

Supporting entities

SUS LIP6 CNRSnew.jpg