Difference between revisions of "FSiC2019"

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The [https://www-soc.lip6.fr/events/pastevents/2018/ second] '''Free Silicon Conference (FSiC)''' will be held at [https://www-soc.lip6.fr/evenements/ Sorbonne Université] (Paris) on '''March 14-16 2019'''. The conference will bring together experts and enthusiasts who want to build a complete Free and Open Source CAD ecosystem for designing analog and digital integrated circuits. The conference will cover the full spectrum of the design process, from system architecture, to layout and verification. The conference consists of three full days, including a Saturday for facilitating those who are involved as non-professionals. After the daily talks, the discussion will continue until late in an informal and relaxed atmosphere at the on-campus [http://www.locations.espaces.upmc.fr/fr/presentation_espaces/campus_jussieu/caves_esclangon.html ''caves Esclangon''].
The [https://www-soc.lip6.fr/events/pastevents/2018/ second] '''Free Silicon Conference (FSiC)''' took place at [https://www-soc.lip6.fr/evenements/ Sorbonne Université] (Paris) on '''March 14-16 2019'''. The conference brought together experts and enthusiasts who want to build a complete Free and Open Source CAD ecosystem for designing analog and digital integrated circuits. The conference covered the full spectrum of the design process, from system architecture, to layout and verification. The conference consisted of three full days, including a Saturday for facilitating those who are involved as non-professionals. After the daily talks, the discussion continued until late in an informal and relaxed atmosphere at the on-campus [http://www.locations.espaces.upmc.fr/fr/presentation_espaces/campus_jussieu/caves_esclangon.html ''caves Esclangon''].


== Abstract submission ==
All '''video recordings''' are available on [https://peertube.f-si.org/video-channels/fsic2019 peertube].
Everybody is welcome to propose a talk by writing to fsic2019 'at' f-si.org. The submission window opened on December 12 2018 and will close on January 31 2019. Acceptance will be communicated by February 10.
 
== Video recordings, slides and documentation ==
All the talks have been recorded and can be watched on [https://peertube.f-si.org/video-channels/fsic2019 peertube]. Extra documentation and the slides of most talks can be found by clicking on the respective titles in the program below.


== Participation ==
== Participation ==
Attending the conference is free of charge. Lunches, dinners and drinks will be offered. However, due to the limited number of spaces available, places must be reserved before February 15 by writing at fsic2019 'at' f-si.org.
Attendance to the conference was free of charge. Lunches, dinners and drinks were offered. However, due to the limited number of spaces available, seats had to be reserved before February *21* by writing at fsic2019 'at' f-si.org.
 
The submission window closed on January 31 2019.


== Organizing committee ==
== Organizing committee ==
* Marie-Minerve Louërat, Lip6, CNRS
* Marie-Minerve Louërat, LIP6, CNRS
* Roselyne Chotin, Lip6, Sorbonne Université
* Roselyne Chotin, LIP6, Sorbonne Université
* Jean-Paul Chaput, Lip6, Sorbonne Université
* Jean-Paul Chaput, LIP6, Sorbonne Université
* Luca Alloatti, ETH-Zurich
* Luca Alloatti, ETH-Zurich
* Matthias Koefferlein, KLayout project
* Matthias Koefferlein, KLayout project
* Sean Cross, Kosagi
* Sean Cross, Kosagi
* Thomas Kramer, ETH-Zurich


== Confirmed invited talks ==
==Conference program==
The speakers below have ''confirmed'' their attendance. Speakers who gave a tentative agreement are not yet included.


'''Day 1'''
=== March 14, Thursday (Day 1) ===
* [https://puri.sm/about/team/ Todd Weaver], ''Title to be announced'', [https://puri.sm Purism]
==== Registration ====
* Mehdi Benchoufi, ''[[The open-source and low-cost echo-stethoscope project]]'', [http://www.echopen.org/ echopen]
* 9:00-9:30, Registration and coffee
* [http://wiring.org.co/about.html Hernando Barragán], ''[[Wiring and visions]]'', [http://wiring.org.co/ Wiring]
* [https://www.cs.hs-rm.de/~reith/ Steffen Reith], ''Title to be announced'', [https://www.hs-rm.de/ Hochschule RheinMain]
* Edmund Humenberger, ''[[ASICone. Goals, timeline, participants and tools]]'', [https://www.symbioticeda.com Symbiotic EDA]
* [http://www-labsticc.univ-ubs.fr/~coussy/ Philippe Coussy], ''[[GAUT]]'', [http://www.gaut.fr/ GAUT], Lab-STICC Université Bretagne Sud
* Tristan Gingold, ''[[GHDL and the economy of EDA FOSS]]'', [http://ghdl.free.fr/ GHDL]
* Frédéric Pétrot, ''[[High level Simulation]]'', [http://tima.imag.fr/sls/ Université Grenoble Alpes and TIMA Laboratory]
* Pirouz Bazargan Sabet, ''[[Functional abstraction]]'', [https://www.lip6.fr/actualite/personnes-fiche.php?ident=P87 Sorbonne Université and LIP6 Laboratory] 
* Charles Papon, ''[[From the RISC-V spec to a low-tech SoC, passing by SpinalHDL, VexRiscv and OpenOCD]]'', [https://github.com/SpinalHDL SpinalHDL]
* Jean Bruant, ''[[State of the art on high-level hardware description languages to generate VHDL or SystemVerilog]]'', [https://www.ovh.com/fr/ OVH] and [http://tima.imag.fr/sls/ TIMA Laboratory]
* Christoph Grimm, ''[[SystemC AMS and upcoming free frameworks for the free design]]'', [https://cps.cs.uni-kl.de/en/staff/christoph-grimm-prof-dr/ Kaiserslautern University]
* [https://www.uni-due.de/person/1998 Holger Vogt], ''[[ngspice - an open source mixed signal circuit simulator]]'', [http://ngspice.sourceforge.net/ ngspice], [http://www.uni-due.de/ebs University Duisburg-Essen]
* Al Davis, ''[[Gnu Circuit Analysis Package (GnuCap)]]'', [https://savannah.gnu.org/git/?group=gnucap GnuCap]
* [http://www.mos-ak.org/wg.html Wladek Grabinski], ''[[MOS-AK FOSS TCAD/EDA Perspective]]'', [http://mos-ak.org/ MOS-AK (EU)]
* Daniela Genius, ''[[Model-Driven Performance Evaluation and Formal Verification for Multi-level Embedded System Design ]]'', [https://www.lip6.fr/actualite/personnes-fiche.php?ident=P96 Sorbonne Université, LIP6]
* Guillaume Delbergue, ''[[Toward a collaborative environment for Open Hardware Design]]'', [https://www.hiventive.com/ Hiventive]


'''Day 2'''
==== Welcome ====
* Jean-Christophe Crébier, ''[[CMP add on services]]'', [https://mycmp.fr/ CMP]
* 9:35-9:45, [https://www.lip6.fr/presentation/directeur.php?LANG=en LIP6] Director [https://www.lip6.fr/actualite/personnes-fiche.php?ident=P182 Fabrice Kordon] ''[[LIP6 Welcome]]''
* Kirti Bhanushali, ''[[Development of FreePDK: An Open-Source Process Design Kit for Advanced Technology Nodes]]'', [https://www.eda.ncsu.edu/wiki/FreePDK NCSU, FreePDK]
* 9:45-9:50, [https://www-soc.lip6.fr/en/team-cian/ CIAN team] within LIP6 ''[[CIAN Team Welcome]]''
* Speaker to be announced, ''[[LibreSilicon]]'', [http://libresilicon.com/ LibreSilicon]
* 9:50-9:55, Welcome from the Free Silicon Foundation
* Thomas Benz, ''[[Converting 45nm transistor netlists to open standards]]'', [https://www.ethz.ch ETH Zurich]
* Naohiko Shimizu, ''[[The development of the NSXLIB standard cell scalable library]]'', [http://labo.nshimizu.com/ Tokai University]
* [https://www.soe.ucsc.edu/people/mrg Matthew Guthaus], ''[[OpenRAM]]'', [https://openram.soe.ucsc.edu/ OpenRAM, UCSC]
* Thomas Kramer, ''[[FOS standard cell generator from scratch]]'', [https://www.ethz.ch ETH Zurich]
* Kay-Uwe Giering, ''[[FET ageing predictions and their coupling to Spice simulations]]'', [https://www.eas.iis.fraunhofer.de/ Fraunhofer IIS/EAS]
* Matthias Köfferlein, ''[[Mask layout database and (new) verification algorithms]]'', [https://klayout.de KLayout]
* Liliana Andrade, ''[[Mixed-signal system modelling and simulation]]'', [http://tima.imag.fr/sls/ Université Grenoble Alpes and TIMA Laboratory]
* Gabriel Gouvine, ''Title to be announced'', [https://www.localsolver.com/ Local Solver]
* Enrico Di Lorenzo, [[Open_Source_Parasitic_Extraction|''Open Source parasitic extraction - solutions, challenges, and business models'']], [http://www.fastfieldsolvers.com FastFieldSolvers]
* Tim Edwards, ''[[The Raven chip: First-time silicon success with qflow and efabless]]'', [http://opencircuitdesign.com/ Open Circuit Design, Qflow]
* Andreas Westerwick, ''[[Libre Silicon Compiler]]'', [http://libresilicon.com/ LibreSilicon]


'''Day 3'''
==== Introduction and motivation for Free and Open Source (FOS) silicon ====
* Mark Burton, ''[[High level system modelling, hands-on computer session]]'', [https://www.greensocs.com/about-us GreenSocs]
* 10:00-10:30, [https://puri.sm/about/team/ Todd Weaver], ''[[The Future of Computing and Why You Should Care]]'', [https://puri.sm Purism]
* [https://www.lip6.fr/actualite/personnes-fiche.php?ident=P109 Jean-Paul Chaput], ''[[The Alliance/Coriolis design flow]]'', [https://www-soc.lip6.fr/equipe-cian/logiciels LIP6]
* 10:30-11:00, [https://www.cs.hs-rm.de/~reith/ Steffen Reith], ''[[Towards digital sovereignty by open source (hardware)]]'', [https://www.hs-rm.de/ Hochschule RheinMain]
* Matthias Köfferlein, ''[[Hands-on with KLayout: Design rule checks and layout to netlist tools]]'', [https://klayout.de KLayout]
* Abhaya Chandra Kammara, ''[[ABSYNTH: Analog Design Automation - An approach to bring VLSI analog design to the hobbyists/non-professionals]]'', []


== Preliminary Program ==
====High-level digital design (session I)====
=== March 14, Thursday (Day 1) ===
* 11:00-11:30, [http://www-labsticc.univ-ubs.fr/~coussy/ Philippe Coussy], ''[[GAUT - A Free and Open-Source High-Level Synthesis tool]]'', [http://www.gaut.fr/ GAUT], Lab-STICC Université Bretagne Sud
==== Introduction ====
* 11:30-12:00, Tristan Gingold, ''[[GHDL and the economy of EDA FOSS]]'', [http://ghdl.free.fr/ GHDL]
* Motivations for Free and Open Source (FOS) hardware
* 12:00-12:30, Frédéric Pétrot, ''[[High level Simulation]]'', [http://tima.imag.fr/sls/ Université Grenoble Alpes and TIMA Laboratory]<br><br>
* Impact on society, academia, makers, industry
* '''12:30-13:30''', '''lunch''' is served at the on-campus [http://www.locations.espaces.upmc.fr/fr/presentation_espaces/campus_jussieu/patio.html Le Patio]<br><br>
* Impact on cybersecurity
* 13:30-14:00, Daniela Genius, ''[[Model-Driven Performance Evaluation and Formal Verification for Multi-level Embedded System Design ]]'', [https://www.lip6.fr/actualite/personnes-fiche.php?ident=P96 Sorbonne Université, LIP6]
* Politics and marketing
* 14:00-14:30, Charles Papon, ''[[From the RISC-V spec to a low-tech SoC, passing by SpinalHDL, VexRiscv and OpenOCD]]'', [https://github.com/SpinalHDL SpinalHDL]
* Business opportunities
* 14:30-15:00, Jean Bruant, ''[[State of the art on high-level hardware description languages to generate VHDL or SystemVerilog]]'', [https://www.ovh.com/fr/ OVH] and [http://tima.imag.fr/sls/ TIMA Laboratory]
* 15:00-15:30, Florent Kermarrec, ''[https://docs.google.com/presentation/d/1KVgzcvEeqLPxYd4PO6zqF0mrlQBP86Vf6CQSiVO81I8/edit?usp=sharing LiteX: an open-source SoC builder and library based on Migen Python DSL]'', [http://enjoy-digital.fr/ Enjoy Digital]


==== High-level system requirements ====
====Mixed-signal/analog design and transistor modelling====
* Case studies from the perspective successful Open Hardware projects
* 15:30-16:00, Christoph Grimm, ''[[SystemC AMS and upcoming free frameworks for the free design]]'', [https://cps.cs.uni-kl.de/en/staff/christoph-grimm-prof-dr/ Kaiserslautern University]<br><br>
* '''16:00-16:30''', '''Afternoon break.''' Coffee is served at the on-campus [http://www.locations.espaces.upmc.fr/fr/presentation_espaces/campus_jussieu/patio.html Le Patio]<br><br>
* 16:30-17:00, Liliana Andrade, ''[[Mixed-signal system modelling and simulation]]'', [http://tima.imag.fr/sls/ Université Grenoble Alpes and TIMA Laboratory]
* 17:00-17:30, [https://www.uni-due.de/person/1998 Holger Vogt], ''[[ngspice - an open source mixed signal circuit simulator]]'', [http://ngspice.sourceforge.net/ ngspice], [http://www.uni-due.de/ebs University Duisburg-Essen]
* 17:30-18:00, Al Davis, ''[[Gnu Circuit Analysis Package (GnuCap)]]'', [https://savannah.gnu.org/git/?group=gnucap GnuCap]
* 18:00-18:30, Felix Salfelder, ''[[GnuCap: Progress and Opportunities]]'', [https://savannah.gnu.org/git/?group=gnucap GnuCap]


==== High-level digital design (architectural and pre-layout) ====
====Evening program "beer & baguette" on-campus====
* Architectural opportunities for FOS Hardware
* 19:00-22:00: drinks are served
* High-level hardware description languages to generate VHDL or SystemVerilog
* 19:30: dinner is served
* Formal verification
* 21:00: end of the day
* High-level virtual prototyping


==== Analog design and simulation ====
=== March 15, Friday (Day 2) ===
* Comparison of FOS tools: Coriolis, qucs, KiCad.
==== Morning Coffee ====
* Ngspice
* 8:30-9:00, Early bird coffee and tea
* SystemC-AMS


=== March 15, Friday (Day 2) ===
==== Impact of FOS hardware ====
==== Foundries ====
* 9:00-9:30, Olivier de Fresnoye, ''[[Open Source in Healthcare, an hardware approach: the echOpen project case]]'', [http://www.echopen.org/ echopen]
* FOS hardware from the foundry's perspective: legal challenges and opportunities
* 9:30-10:00, Edmund Humenberger, ''[[ASICone. Goals, timeline, participants and tools]]'', [https://www.symbioticeda.com Symbiotic EDA]
* MakeLSI
* 10:00-10:30, Staf Verhaegen, ''[[Lesson learned from Retro-uC and the search for the ideal EDA flow for open source silicon]]'', [https://www.chips4makers.io/blog Chips4Makers]


==== Setting up the ingredients ====
====Foundries, PDKs and cell libraries====
* Importing PDKs into FOS formats
* 10:30-11:00, Jean-Christophe Crébier, Kholdoun Torki, ''[[CMP add on services - Towards Foundry PDKs on Free CAD Tools]]'', [https://mycmp.fr/ CMP]
* Standard cell: generators and modelling
* 11:00-11:30, Kirti Bhanushali, ''[[Development of FreePDK: An Open-Source Process Design Kit for Advanced Technology Nodes]]'', [https://www.eda.ncsu.edu/wiki/FreePDK NCSU, FreePDK]
* Parametrized analog devices and topologies
* 11:30-12:00, Thomas Benz, ''[[Converting 45nm transistor netlists to open standards]]'', [https://www.ethz.ch ETH Zurich]
* Parametrized Optical devices
* 12:00-12:30, Naohiko Shimizu, ''[[The development of the NSXLIB standard cell scalable library]]'', [http://labo.nshimizu.com/ Tokai University]<br><br>
* Memory generators
* '''12:30-13:30''', '''lunch''' is served at the on-campus [http://www.locations.espaces.upmc.fr/fr/presentation_espaces/campus_jussieu/patio.html Le Patio]<br><br>
* 13:30-14:00, Hagen Sankowski, ''[[Popcorn - or how many cells your Standard Cell Library has?]]'', [http://libresilicon.com/ LibreSilicon]
* 14:00-14:30, [https://www.soe.ucsc.edu/people/mrg Matthew Guthaus], ''[[OpenRAM: An Open-Source Memory Compiler]]'', [https://vlsida.github.io/OpenRAM/ OpenRAM], UCSC
* 14:30-15:00, Thomas Kramer, ''[[FOS standard cell generator from scratch]]'', [https://www.ethz.ch ETH Zurich]


==== CAD internals and algorithms - how the tools work ====
====Back-end flow and algorithms====
* The role of databases
* 15:00-15:30, Gabriel Gouvine, ''[[Placement algorithms for standard cells in Coriolis]]'', [https://www.localsolver.com/ Local Solver]
* Place algorithms
* 15:30-16:00, Matthias Köfferlein, ''[[KLayout's deep verification base project]]'', [https://klayout.de KLayout]<br><br>
* Routing algorithms, global and detailed
* '''16:00-16:30''', '''Afternoon break.''' Coffee is served at the on-campus [http://www.locations.espaces.upmc.fr/fr/presentation_espaces/campus_jussieu/patio.html Le Patio]<br><br>
* Timing analysis
* 16:30-17:00, Pirouz Bazargan Sabet, ''[[Functional abstraction]]'', [https://www.lip6.fr/actualite/personnes-fiche.php?ident=P87 Sorbonne Université and LIP6 Laboratory]
* Power analysis
* 17:00-17:30, Enrico Di Lorenzo, [[Open_Source_Parasitic_Extraction|''Open Source parasitic extraction - solutions, challenges, and business models'']], [http://www.fastfieldsolvers.com FastFieldSolvers]
* Formal VHDL verification
* 17:30-18:00, Tim Edwards, ''[[The Raven chip: First-time silicon success with qflow and efabless]]'', [http://opencircuitdesign.com/ Open Circuit Design, Qflow]
* 18:00-18:30, Hagen Sankowski, ''[[Somebody is using the Advanced Library Format (ALF)? We like to do!]]'', [http://libresilicon.com/ LibreSilicon]


==== Legal issues ====
====Evening program "beer & baguette" at the on-campus Tour Zamansky, 24th floor (room with a view)====
* The constrains of typical NDAs
* 18:30-21:00: drinks are served
* Hardware FOS licenses. State-of-the-art
* 19:30: dinner is served
* 21:00: end of the day


=== March 16, Saturday (Day 3) ===
=== March 16, Saturday (Day 3) ===
==== CAD tool usage - demos ====
==== Morning Coffee ====
* Synthesis
* 8:30-9:00, Early bird coffee and tea
* Place and route tools
* Timing analysis
* Clock distribution


==== Post place-and-route (P&R) verification and simulators ====
====Licenses====
* Design Rule Check
* 9:00-9:30, Tristan Gingold, ''[[CERN OHL v2 draft]]'', [https://www.ohwr.org/project/cernohl/wikis/CERN-OHL-v2-draft CERN]
* LVS
* Static Timing Analysis
* Fault modelling and Automatic Test Pattern Generators (ATPG)


==== Workshop ====
====High-level digital design (session II)====
Further topics and questions raised during the conference will be discussed in plenary or in individual working groups.
* 9:30-10:00, Guillaume Delbergue, ''[[Toward a collaborative environment for Open Hardware Design]]'', [https://www.hiventive.com/ Hiventive]
* 10:00-11:00, Frédéric Pétrot, ''[[High level system modelling, hands-on computer session]]'', [https://www.greensocs.com/about-us GreenSocs], '''(Tutorial)'''


== Time schedule ==
====Analog back-end design====
===Day 1===
* 11:00-11:30, Marie-Minerve Louërat, ''[[From filters to CMOS transistors - A library of analog schematics with automated sizing]]'', [https://www-soc.lip6.fr/en/team-cian/ LIP6]
* 11:30-12:00, Abhaya Chandra Kammara, ''[[ABSYNTH: Analog Design Automation - An approach to bring VLSI analog design to the hobbyists/non-professionals]]'', [https://www.eit.uni-kl.de/koenig/gemeinsame_seiten/projects/Research%20Projects.htm TU Kaiserslautern]
* 12:00-12:30, discussions<br><br>
* '''12:30-13:30''', '''lunch''' is served at the on-campus [http://www.locations.espaces.upmc.fr/fr/presentation_espaces/campus_jussieu/patio.html Le Patio]


On the first day the talks begin later for allowing some people to travel in the morning.
====Back-end design====
* 9:00: registration opens
* 13:30-14:30, [https://www.lip6.fr/actualite/personnes-fiche.php?ident=P109 Jean-Paul Chaput], ''[[The Alliance/Coriolis design flow]]'', [https://www-soc.lip6.fr/equipe-cian/logiciels LIP6], '''(Tutorial)'''
* 9:30: welcome
* 14:30-15:45, Matthias Köfferlein, ''[[Hands-on with KLayout: Design rule checks and layout to netlist tools]]'', [https://klayout.de KLayout], '''(Tutorial)'''
* 10:00: first session
* 15:45-16:00, conclusions
* 12:30-13:30: lunch is served at the on-campus [http://www.locations.espaces.upmc.fr/fr/presentation_espaces/campus_jussieu/patio.html Le Patio]
* 18:30: end of last session
 
* 18:30-19:30: break
 
The evening program "beer & baguette" continues at the on-campus [http://www.locations.espaces.upmc.fr/fr/presentation_espaces/campus_jussieu/caves_esclangon.html ''caves Esclangon'']
* 18:30-23:00: drinks are served
* 19:30: dinner is served
* 23:00: end of the day
 
===Day 2===
* 9:00: first session
* 12:30-13:30: lunch is served at the on-campus [http://www.locations.espaces.upmc.fr/fr/presentation_espaces/campus_jussieu/patio.html Le Patio]
* 18:30: end of last session
 
* 18:30-19:30: break
 
The evening program "beer & baguette" continues at the on-campus [http://www.locations.espaces.upmc.fr/fr/presentation_espaces/campus_jussieu/caves_esclangon.html ''caves Esclangon'']
* 18:30-23:00: drinks are served
* 19:30: dinner is served
* 23:00: end of the day
 
===Day 3===
* 9:00: first session
* 12:30-13:30: lunch is served at the on-campus [http://www.locations.espaces.upmc.fr/fr/presentation_espaces/campus_jussieu/patio.html Le Patio]
* 16:00: end of last session


== Practical information ==
== Practical information ==
Line 169: Line 126:
*[[Guidelines for invited speakers]]
*[[Guidelines for invited speakers]]
*[[Mediawiki template for invited speakers]]
*[[Mediawiki template for invited speakers]]
==Supporting entities==
[[File:SUS_LIP6_CNRSnew.jpg|500px]]

Revision as of 14:10, 17 April 2019

Free Silicon Conference 2019
Fsic2019 logo.svg
GenreFree software and free hardware development conference
Location(s)Paris, Sorbonne Université
CountryFrance
Websitewiki.f-si.org/index.php/FSiC2019

The second Free Silicon Conference (FSiC) took place at Sorbonne Université (Paris) on March 14-16 2019. The conference brought together experts and enthusiasts who want to build a complete Free and Open Source CAD ecosystem for designing analog and digital integrated circuits. The conference covered the full spectrum of the design process, from system architecture, to layout and verification. The conference consisted of three full days, including a Saturday for facilitating those who are involved as non-professionals. After the daily talks, the discussion continued until late in an informal and relaxed atmosphere at the on-campus caves Esclangon.

All video recordings are available on peertube.

Video recordings, slides and documentation

All the talks have been recorded and can be watched on peertube. Extra documentation and the slides of most talks can be found by clicking on the respective titles in the program below.

Participation

Attendance to the conference was free of charge. Lunches, dinners and drinks were offered. However, due to the limited number of spaces available, seats had to be reserved before February *21* by writing at fsic2019 'at' f-si.org.

The submission window closed on January 31 2019.

Organizing committee

  • Marie-Minerve Louërat, LIP6, CNRS
  • Roselyne Chotin, LIP6, Sorbonne Université
  • Jean-Paul Chaput, LIP6, Sorbonne Université
  • Luca Alloatti, ETH-Zurich
  • Matthias Koefferlein, KLayout project
  • Sean Cross, Kosagi
  • Thomas Kramer, ETH-Zurich

Conference program

March 14, Thursday (Day 1)

Registration

  • 9:00-9:30, Registration and coffee

Welcome

Introduction and motivation for Free and Open Source (FOS) silicon

High-level digital design (session I)

Mixed-signal/analog design and transistor modelling

Evening program "beer & baguette" on-campus

  • 19:00-22:00: drinks are served
  • 19:30: dinner is served
  • 21:00: end of the day

March 15, Friday (Day 2)

Morning Coffee

  • 8:30-9:00, Early bird coffee and tea

Impact of FOS hardware

Foundries, PDKs and cell libraries

Back-end flow and algorithms

Evening program "beer & baguette" at the on-campus Tour Zamansky, 24th floor (room with a view)

  • 18:30-21:00: drinks are served
  • 19:30: dinner is served
  • 21:00: end of the day

March 16, Saturday (Day 3)

Morning Coffee

  • 8:30-9:00, Early bird coffee and tea

Licenses

High-level digital design (session II)

Analog back-end design

Back-end design

Practical information

Supporting entities

SUS LIP6 CNRSnew.jpg