Difference between revisions of "FSiC2019"

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==== Introduction and motivation for Free and Open Source (FOS) silicon ====
==== Introduction and motivation for Free and Open Source (FOS) silicon ====
* 10:00-10:30, [https://puri.sm/about/team/ Todd Weaver], ''Title to be announced'', [https://puri.sm Purism]
* 10:00-10:30, [https://puri.sm/about/team/ Todd Weaver], ''[[The Future of Computing and Why You Should Care]]'', [https://puri.sm Purism]
* 10:30-11:00, [https://www.cs.hs-rm.de/~reith/ Steffen Reith], ''[[Towards digital sovereignty by open source (hardware)]]'', [https://www.hs-rm.de/ Hochschule RheinMain]
* 10:30-11:00, [https://www.cs.hs-rm.de/~reith/ Steffen Reith], ''[[Towards digital sovereignty by open source (hardware)]]'', [https://www.hs-rm.de/ Hochschule RheinMain]


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* 14:00-14:30, Charles Papon, ''[[From the RISC-V spec to a low-tech SoC, passing by SpinalHDL, VexRiscv and OpenOCD]]'', [https://github.com/SpinalHDL SpinalHDL]
* 14:00-14:30, Charles Papon, ''[[From the RISC-V spec to a low-tech SoC, passing by SpinalHDL, VexRiscv and OpenOCD]]'', [https://github.com/SpinalHDL SpinalHDL]
* 14:30-15:00, Jean Bruant, ''[[State of the art on high-level hardware description languages to generate VHDL or SystemVerilog]]'', [https://www.ovh.com/fr/ OVH] and [http://tima.imag.fr/sls/ TIMA Laboratory]
* 14:30-15:00, Jean Bruant, ''[[State of the art on high-level hardware description languages to generate VHDL or SystemVerilog]]'', [https://www.ovh.com/fr/ OVH] and [http://tima.imag.fr/sls/ TIMA Laboratory]
* 15:00-15:30, Florent Kermarrec, ''[[LiteX: an open-source SoC builder and libraty based on Migen Python DSL]]'', [http://enjoy-digital.fr/ Enjoy Digital]
* 15:00-15:30, Florent Kermarrec, ''[https://docs.google.com/presentation/d/1KVgzcvEeqLPxYd4PO6zqF0mrlQBP86Vf6CQSiVO81I8/edit?usp=sharing LiteX: an open-source SoC builder and library based on Migen Python DSL]'', [http://enjoy-digital.fr/ Enjoy Digital]


====Mixed-signal/analog design and transistor modelling====
====Mixed-signal/analog design and transistor modelling====
* 15:30-16:00, Christoph Grimm, ''[[SystemC AMS and upcoming free frameworks for the free design]]'', [https://cps.cs.uni-kl.de/en/staff/christoph-grimm-prof-dr/ Kaiserslautern University]<br><br>
* 15:30-16:00, Christoph Grimm, ''[[SystemC AMS and upcoming free frameworks for the free design]]'', [https://cps.cs.uni-kl.de/en/staff/christoph-grimm-prof-dr/ Kaiserslautern University]<br><br>
* '''16:00-16:30''', '''Afternoon break.''' Coffee is served at the on-campus [http://www.locations.espaces.upmc.fr/fr/presentation_espaces/campus_jussieu/patio.html Le Patio]<br><br>
* '''16:00-16:30''', '''Afternoon break.''' Coffee is served at the on-campus [http://www.locations.espaces.upmc.fr/fr/presentation_espaces/campus_jussieu/patio.html Le Patio]<br><br>
* 16:00-16:30, Liliana Andrade, ''[[Mixed-signal system modelling and simulation]]'', [http://tima.imag.fr/sls/ Université Grenoble Alpes and TIMA Laboratory]
* 16:30-17:00, Liliana Andrade, ''[[Mixed-signal system modelling and simulation]]'', [http://tima.imag.fr/sls/ Université Grenoble Alpes and TIMA Laboratory]
* 17:00-17:30, [https://www.uni-due.de/person/1998 Holger Vogt], ''[[ngspice - an open source mixed signal circuit simulator]]'', [http://ngspice.sourceforge.net/ ngspice], [http://www.uni-due.de/ebs University Duisburg-Essen]
* 17:00-17:30, [https://www.uni-due.de/person/1998 Holger Vogt], ''[[ngspice - an open source mixed signal circuit simulator]]'', [http://ngspice.sourceforge.net/ ngspice], [http://www.uni-due.de/ebs University Duisburg-Essen]
* 17:30-18:00, Al Davis, ''[[Gnu Circuit Analysis Package (GnuCap)]]'', [https://savannah.gnu.org/git/?group=gnucap GnuCap]
* 17:30-18:00, Al Davis, ''[[Gnu Circuit Analysis Package (GnuCap)]]'', [https://savannah.gnu.org/git/?group=gnucap GnuCap]
* 18:00-18:30, Felix Salfelder, ''[[GnuCap: Progress and Opportunities]]'', [https://savannah.gnu.org/git/?group=gnucap GnuCap]
* 18:00-18:30, Felix Salfelder, ''[[GnuCap: Progress and Opportunities]]'', [https://savannah.gnu.org/git/?group=gnucap GnuCap]
* 18:30-19:00, [http://www.mos-ak.org/wg.html Wladek Grabinski], ''[[MOS-AK FOSS TCAD/EDA Perspective]]'', [http://mos-ak.org/ MOS-AK (EU)]


====Evening program "beer & baguette" at the on-campus [http://www.locations.espaces.upmc.fr/fr/presentation_espaces/campus_jussieu/caves_esclangon.html ''caves Esclangon'']====
====Evening program "beer & baguette" on-campus====
* 19:00-22:00: drinks are served
* 19:00-22:00: drinks are served
* 19:30: dinner is served
* 19:30: dinner is served
* 22:30: end of the day
* 21:00: end of the day


=== March 15, Friday (Day 2) ===
=== March 15, Friday (Day 2) ===
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* 9:00-9:30, Olivier de Fresnoye, ''[[Open Source in Healthcare, an hardware approach: the echOpen project case]]'', [http://www.echopen.org/ echopen]
* 9:00-9:30, Olivier de Fresnoye, ''[[Open Source in Healthcare, an hardware approach: the echOpen project case]]'', [http://www.echopen.org/ echopen]
* 9:30-10:00, Edmund Humenberger, ''[[ASICone. Goals, timeline, participants and tools]]'', [https://www.symbioticeda.com Symbiotic EDA]
* 9:30-10:00, Edmund Humenberger, ''[[ASICone. Goals, timeline, participants and tools]]'', [https://www.symbioticeda.com Symbiotic EDA]
* 10:00-10:30, Staf Verhaegen, ''[[Lesson learned from Retro-uC and search for ideal HDL for open source silicon]]''
* 10:00-10:30, Staf Verhaegen, ''[[Lesson learned from Retro-uC and the search for the ideal EDA flow for open source silicon]]'', [https://www.chips4makers.io/blog Chips4Makers]


====Foundries, PDKs and cell libraries====
====Foundries, PDKs and cell libraries====
* 10:30-11:00, Jean-Christophe Crébier, ''[[CMP add on services]]'', [https://mycmp.fr/ CMP]
* 10:30-11:00, Jean-Christophe Crébier, Kholdoun Torki, ''[[CMP add on services - Towards Foundry PDKs on Free CAD Tools]]'', [https://mycmp.fr/ CMP]
* 11:00-11:30, Kirti Bhanushali, ''[[Development of FreePDK: An Open-Source Process Design Kit for Advanced Technology Nodes]]'', [https://www.eda.ncsu.edu/wiki/FreePDK NCSU, FreePDK]
* 11:00-11:30, Kirti Bhanushali, ''[[Development of FreePDK: An Open-Source Process Design Kit for Advanced Technology Nodes]]'', [https://www.eda.ncsu.edu/wiki/FreePDK NCSU, FreePDK]
* 11:30-12:00, Thomas Benz, ''[[Converting 45nm transistor netlists to open standards]]'', [https://www.ethz.ch ETH Zurich]
* 11:30-12:00, Thomas Benz, ''[[Converting 45nm transistor netlists to open standards]]'', [https://www.ethz.ch ETH Zurich]
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* '''12:30-13:30''', '''lunch''' is served at the on-campus [http://www.locations.espaces.upmc.fr/fr/presentation_espaces/campus_jussieu/patio.html Le Patio]<br><br>
* '''12:30-13:30''', '''lunch''' is served at the on-campus [http://www.locations.espaces.upmc.fr/fr/presentation_espaces/campus_jussieu/patio.html Le Patio]<br><br>
* 13:30-14:00, Hagen Sankowski, ''[[Popcorn - or how many cells your Standard Cell Library has?]]'', [http://libresilicon.com/ LibreSilicon]
* 13:30-14:00, Hagen Sankowski, ''[[Popcorn - or how many cells your Standard Cell Library has?]]'', [http://libresilicon.com/ LibreSilicon]
* 14:00-14:30, [https://www.soe.ucsc.edu/people/mrg Matthew Guthaus], ''[[OpenRAM]]'', [https://openram.soe.ucsc.edu/ OpenRAM, UCSC]
* 14:00-14:30, [https://www.soe.ucsc.edu/people/mrg Matthew Guthaus], ''[[OpenRAM: An Open-Source Memory Compiler]]'', [https://vlsida.github.io/OpenRAM/ OpenRAM], UCSC
* 14:30-15:00, Thomas Kramer, ''[[FOS standard cell generator from scratch]]'', [https://www.ethz.ch ETH Zurich]
* 14:30-15:00, Thomas Kramer, ''[[FOS standard cell generator from scratch]]'', [https://www.ethz.ch ETH Zurich]


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* 18:30-19:00, Hagen Sankowski, ''[[Somebody is using the Advanced Library Format (ALF)? We like to do!]]'', [http://libresilicon.com/ LibreSilicon]
* 18:30-19:00, Hagen Sankowski, ''[[Somebody is using the Advanced Library Format (ALF)? We like to do!]]'', [http://libresilicon.com/ LibreSilicon]


====Evening program "beer & baguette" at the on-campus [http://www.locations.espaces.upmc.fr/fr/presentation_espaces/campus_jussieu/caves_esclangon.html ''caves Esclangon'']====
====Evening program "beer & baguette" at the on-campus Tour Zamansky, 24th floor (room with a view)====
* 19:00-22:00: drinks are served
* 18:30-21:00: drinks are served
* 19:30: dinner is served
* 19:30: dinner is served
* 22:30: end of the day
* 21:00: end of the day


=== March 16, Saturday (Day 3) ===
=== March 16, Saturday (Day 3) ===
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* 9:00-9:30, Tristan Gingold, ''[[CERN OHL v2 draft]]'', [https://www.ohwr.org/project/cernohl/wikis/CERN-OHL-v2-draft CERN]
* 9:00-9:30, Tristan Gingold, ''[[CERN OHL v2 draft]]'', [https://www.ohwr.org/project/cernohl/wikis/CERN-OHL-v2-draft CERN]


====High-level digital design (session III)====
====High-level digital design (session II)====
* 9:30-10:00, Guillaume Delbergue, ''[[Toward a collaborative environment for Open Hardware Design]]'', [https://www.hiventive.com/ Hiventive]
* 9:30-10:00, Guillaume Delbergue, ''[[Toward a collaborative environment for Open Hardware Design]]'', [https://www.hiventive.com/ Hiventive]
* 10:00-11:00, Mark Burton, ''[[High level system modelling, hands-on computer session]]'', [https://www.greensocs.com/about-us GreenSocs], '''(Tutorial)'''
* 10:00-11:00, Frédéric Pétrot, ''[[High level system modelling, hands-on computer session]]'', [https://www.greensocs.com/about-us GreenSocs], '''(Tutorial)'''


====Analog back-end design====
====Analog back-end design====

Revision as of 14:45, 18 March 2019

Free Silicon Conference 2019
Fsic2019 logo.svg
GenreFree software and free hardware development conference
Location(s)Paris, Sorbonne Université
CountryFrance
Websitewiki.f-si.org/index.php/FSiC2019

The second Free Silicon Conference (FSiC) will be held at Sorbonne Université (Paris) on March 14-16 2019. The conference will bring together experts and enthusiasts who want to build a complete Free and Open Source CAD ecosystem for designing analog and digital integrated circuits. The conference will cover the full spectrum of the design process, from system architecture, to layout and verification. The conference consists of three full days, including a Saturday for facilitating those who are involved as non-professionals. After the daily talks, the discussion will continue until late in an informal and relaxed atmosphere at the on-campus caves Esclangon.

Participation

Attending the conference is free of charge. Lunches, dinners and drinks will be offered. However, due to the limited number of spaces available, seats must be reserved before February *21* by writing at fsic2019 'at' f-si.org.

The submission window closed on January 31 2019.

Organizing committee

  • Marie-Minerve Louërat, Lip6, CNRS
  • Roselyne Chotin, Lip6, Sorbonne Université
  • Jean-Paul Chaput, Lip6, Sorbonne Université
  • Luca Alloatti, ETH-Zurich
  • Matthias Koefferlein, KLayout project
  • Sean Cross, Kosagi
  • Thomas Kramer, ETH-Zurich

Conference program

March 14, Thursday (Day 1)

Registration

  • 9:00-9:30, Registration and coffee

Welcome

Introduction and motivation for Free and Open Source (FOS) silicon

High-level digital design (session I)

Mixed-signal/analog design and transistor modelling

Evening program "beer & baguette" on-campus

  • 19:00-22:00: drinks are served
  • 19:30: dinner is served
  • 21:00: end of the day

March 15, Friday (Day 2)

Morning Coffee

  • 8:30-9:00, Early bird coffee and tea

Impact of FOS hardware

Foundries, PDKs and cell libraries

Back-end flow and algorithms

Evening program "beer & baguette" at the on-campus Tour Zamansky, 24th floor (room with a view)

  • 18:30-21:00: drinks are served
  • 19:30: dinner is served
  • 21:00: end of the day

March 16, Saturday (Day 3)

Morning Coffee

  • 8:30-9:00, Early bird coffee and tea

Licenses

High-level digital design (session II)

Analog back-end design

Back-end design

Practical information

Supporting entities

LIP6 SU CNRS logo.jpg