Difference between revisions of "FSiC2019"

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=== March 14, Thursday (Day 1) ===
=== March 14, Thursday (Day 1) ===
==== Registration ====
* 9:00-9:30, Registration and coffee
==== Welcome ====
==== Welcome ====
* [https://www.lip6.fr/presentation/directeur.php?LANG=en LIP6] Director [https://www.lip6.fr/actualite/personnes-fiche.php?ident=P182 Fabrice Kordon]
* 9:35-9:45, [https://www.lip6.fr/presentation/directeur.php?LANG=en LIP6] Director [https://www.lip6.fr/actualite/personnes-fiche.php?ident=P182 Fabrice Kordon]
* [https://www-soc.lip6.fr/en/team-cian/ CIAN team] within LIP6
* 9:45-9:50, [https://www-soc.lip6.fr/en/team-cian/ CIAN team] within LIP6
* 9:50-9:55, Welcome from the Free Silicon Foundation


==== Introduction and motivation for Free and Open Source (FOS) silicon ====
==== Introduction and motivation for Free and Open Source (FOS) silicon ====
* [https://puri.sm/about/team/ Todd Weaver], ''Title to be announced'', [https://puri.sm Purism]
* 10:00-10:30, [https://puri.sm/about/team/ Todd Weaver], ''[[The Future of Computing and Why You Should Care]]'', [https://puri.sm Purism]
* [https://www.cs.hs-rm.de/~reith/ Steffen Reith], ''[[Towards digital sovereignty by open source (hardware)]]'', [https://www.hs-rm.de/ Hochschule RheinMain]
* 10:30-11:00, [https://www.cs.hs-rm.de/~reith/ Steffen Reith], ''[[Towards digital sovereignty by open source (hardware)]]'', [https://www.hs-rm.de/ Hochschule RheinMain]


====High-level digital design (session I)====
====High-level digital design (session I)====
* [http://www-labsticc.univ-ubs.fr/~coussy/ Philippe Coussy], ''[[GAUT]]'', [http://www.gaut.fr/ GAUT], Lab-STICC Université Bretagne Sud
* 11:00-11:30, [http://www-labsticc.univ-ubs.fr/~coussy/ Philippe Coussy], ''[[GAUT - A Free and Open-Source High-Level Synthesis tool]]'', [http://www.gaut.fr/ GAUT], Lab-STICC Université Bretagne Sud
* Tristan Gingold, ''[[GHDL and the economy of EDA FOSS]]'', [http://ghdl.free.fr/ GHDL]
* 11:30-12:00, Tristan Gingold, ''[[GHDL and the economy of EDA FOSS]]'', [http://ghdl.free.fr/ GHDL]
* Frédéric Pétrot, ''[[High level Simulation]]'', [http://tima.imag.fr/sls/ Université Grenoble Alpes and TIMA Laboratory]
* 12:00-12:30, Frédéric Pétrot, ''[[High level Simulation]]'', [http://tima.imag.fr/sls/ Université Grenoble Alpes and TIMA Laboratory]<br><br>
* Daniela Genius, ''[[Model-Driven Performance Evaluation and Formal Verification for Multi-level Embedded System Design ]]'', [https://www.lip6.fr/actualite/personnes-fiche.php?ident=P96 Sorbonne Université, LIP6]
* '''12:30-13:30''', '''lunch''' is served at the on-campus [http://www.locations.espaces.upmc.fr/fr/presentation_espaces/campus_jussieu/patio.html Le Patio]<br><br>
* Charles Papon, ''[[From the RISC-V spec to a low-tech SoC, passing by SpinalHDL, VexRiscv and OpenOCD]]'', [https://github.com/SpinalHDL SpinalHDL]
* 13:30-14:00, Daniela Genius, ''[[Model-Driven Performance Evaluation and Formal Verification for Multi-level Embedded System Design ]]'', [https://www.lip6.fr/actualite/personnes-fiche.php?ident=P96 Sorbonne Université, LIP6]
* Jean Bruant, ''[[State of the art on high-level hardware description languages to generate VHDL or SystemVerilog]]'', [https://www.ovh.com/fr/ OVH] and [http://tima.imag.fr/sls/ TIMA Laboratory]
* 14:00-14:30, Charles Papon, ''[[From the RISC-V spec to a low-tech SoC, passing by SpinalHDL, VexRiscv and OpenOCD]]'', [https://github.com/SpinalHDL SpinalHDL]
* 14:30-15:00, Jean Bruant, ''[[State of the art on high-level hardware description languages to generate VHDL or SystemVerilog]]'', [https://www.ovh.com/fr/ OVH] and [http://tima.imag.fr/sls/ TIMA Laboratory]
* 15:00-15:30, Florent Kermarrec, ''[https://docs.google.com/presentation/d/1KVgzcvEeqLPxYd4PO6zqF0mrlQBP86Vf6CQSiVO81I8/edit?usp=sharing LiteX: an open-source SoC builder and library based on Migen Python DSL]'', [http://enjoy-digital.fr/ Enjoy Digital]


====Mixed-signal/analog design and transistor modelling====
====Mixed-signal/analog design and transistor modelling====
* Christoph Grimm, ''[[SystemC AMS and upcoming free frameworks for the free design]]'', [https://cps.cs.uni-kl.de/en/staff/christoph-grimm-prof-dr/ Kaiserslautern University]
* 15:30-16:00, Christoph Grimm, ''[[SystemC AMS and upcoming free frameworks for the free design]]'', [https://cps.cs.uni-kl.de/en/staff/christoph-grimm-prof-dr/ Kaiserslautern University]<br><br>
* Liliana Andrade, ''[[Mixed-signal system modelling and simulation]]'', [http://tima.imag.fr/sls/ Université Grenoble Alpes and TIMA Laboratory]
* '''16:00-16:30''', '''Afternoon break.''' Coffee is served at the on-campus [http://www.locations.espaces.upmc.fr/fr/presentation_espaces/campus_jussieu/patio.html Le Patio]<br><br>
* [https://www.uni-due.de/person/1998 Holger Vogt], ''[[ngspice - an open source mixed signal circuit simulator]]'', [http://ngspice.sourceforge.net/ ngspice], [http://www.uni-due.de/ebs University Duisburg-Essen]
* 16:30-17:00, Liliana Andrade, ''[[Mixed-signal system modelling and simulation]]'', [http://tima.imag.fr/sls/ Université Grenoble Alpes and TIMA Laboratory]
* Al Davis, ''[[Gnu Circuit Analysis Package (GnuCap)]]'', [https://savannah.gnu.org/git/?group=gnucap GnuCap]
* 17:00-17:30, [https://www.uni-due.de/person/1998 Holger Vogt], ''[[ngspice - an open source mixed signal circuit simulator]]'', [http://ngspice.sourceforge.net/ ngspice], [http://www.uni-due.de/ebs University Duisburg-Essen]
* Felix Salfelder, ''[[GnuCap: Progress and Opportunities]]'', [https://savannah.gnu.org/git/?group=gnucap GnuCap]
* 17:30-18:00, Al Davis, ''[[Gnu Circuit Analysis Package (GnuCap)]]'', [https://savannah.gnu.org/git/?group=gnucap GnuCap]
* [http://www.mos-ak.org/wg.html Wladek Grabinski], ''[[MOS-AK FOSS TCAD/EDA Perspective]]'', [http://mos-ak.org/ MOS-AK (EU)]
* 18:00-18:30, Felix Salfelder, ''[[GnuCap: Progress and Opportunities]]'', [https://savannah.gnu.org/git/?group=gnucap GnuCap]
 
====Evening program "beer & baguette" on-campus====
* 19:00-22:00: drinks are served
* 19:30: dinner is served
* 21:00: end of the day


=== March 15, Friday (Day 2) ===
=== March 15, Friday (Day 2) ===
==== Morning Coffee ====
* 8:30-9:00, Early bird coffee and tea
==== Impact of FOS hardware ====
==== Impact of FOS hardware ====
* Olivier de Fresnoye, ''[[Open Source in Healthcare, an hardware approach: the echOpen project case]]'', [http://www.echopen.org/ echopen]
* 9:00-9:30, Olivier de Fresnoye, ''[[Open Source in Healthcare, an hardware approach: the echOpen project case]]'', [http://www.echopen.org/ echopen]
* Edmund Humenberger, ''[[ASICone. Goals, timeline, participants and tools]]'', [https://www.symbioticeda.com Symbiotic EDA]
* 9:30-10:00, Edmund Humenberger, ''[[ASICone. Goals, timeline, participants and tools]]'', [https://www.symbioticeda.com Symbiotic EDA]
* 10:00-10:30, Staf Verhaegen, ''[[Lesson learned from Retro-uC and the search for the ideal EDA flow for open source silicon]]'', [https://www.chips4makers.io/blog Chips4Makers]


====Foundries, PDKs and cell libraries====
====Foundries, PDKs and cell libraries====
* Jean-Christophe Crébier, ''[[CMP add on services]]'', [https://mycmp.fr/ CMP]
* 10:30-11:00, Jean-Christophe Crébier, Kholdoun Torki, ''[[CMP add on services - Towards Foundry PDKs on Free CAD Tools]]'', [https://mycmp.fr/ CMP]
* Kirti Bhanushali, ''[[Development of FreePDK: An Open-Source Process Design Kit for Advanced Technology Nodes]]'', [https://www.eda.ncsu.edu/wiki/FreePDK NCSU, FreePDK]
* 11:00-11:30, Kirti Bhanushali, ''[[Development of FreePDK: An Open-Source Process Design Kit for Advanced Technology Nodes]]'', [https://www.eda.ncsu.edu/wiki/FreePDK NCSU, FreePDK]
* Thomas Benz, ''[[Converting 45nm transistor netlists to open standards]]'', [https://www.ethz.ch ETH Zurich]
* 11:30-12:00, Thomas Benz, ''[[Converting 45nm transistor netlists to open standards]]'', [https://www.ethz.ch ETH Zurich]
* Hagen Sankowski, ''[[Popcorn - or how many cells your Standard Cell Library has?]]'', [http://libresilicon.com/ LibreSilicon]
* 12:00-12:30, Naohiko Shimizu, ''[[The development of the NSXLIB standard cell scalable library]]'', [http://labo.nshimizu.com/ Tokai University]<br><br>
* Naohiko Shimizu, ''[[The development of the NSXLIB standard cell scalable library]]'', [http://labo.nshimizu.com/ Tokai University]
* '''12:30-13:30''', '''lunch''' is served at the on-campus [http://www.locations.espaces.upmc.fr/fr/presentation_espaces/campus_jussieu/patio.html Le Patio]<br><br>
* [https://www.soe.ucsc.edu/people/mrg Matthew Guthaus], ''[[OpenRAM]]'', [https://openram.soe.ucsc.edu/ OpenRAM, UCSC]
* 13:30-14:00, Hagen Sankowski, ''[[Popcorn - or how many cells your Standard Cell Library has?]]'', [http://libresilicon.com/ LibreSilicon]
* Thomas Kramer, ''[[FOS standard cell generator from scratch]]'', [https://www.ethz.ch ETH Zurich]
* 14:00-14:30, [https://www.soe.ucsc.edu/people/mrg Matthew Guthaus], ''[[OpenRAM: An Open-Source Memory Compiler]]'', [https://vlsida.github.io/OpenRAM/ OpenRAM], UCSC
* 14:30-15:00, Thomas Kramer, ''[[FOS standard cell generator from scratch]]'', [https://www.ethz.ch ETH Zurich]


====Back-end flow and algorithms====
====Back-end flow and algorithms====
* Gabriel Gouvine, ''[[Placement algorithms for standard cells in Coriolis]]'', [https://www.localsolver.com/ Local Solver]
* 15:00-15:30, Gabriel Gouvine, ''[[Placement algorithms for standard cells in Coriolis]]'', [https://www.localsolver.com/ Local Solver]
* Matthias Köfferlein, ''[[KLayout's deep verification base project]]'', [https://klayout.de KLayout]
* 15:30-16:00, Matthias Köfferlein, ''[[KLayout's deep verification base project]]'', [https://klayout.de KLayout]<br><br>
* Pirouz Bazargan Sabet, ''[[Functional abstraction]]'', [https://www.lip6.fr/actualite/personnes-fiche.php?ident=P87 Sorbonne Université and LIP6 Laboratory]
* '''16:00-16:30''', '''Afternoon break.''' Coffee is served at the on-campus [http://www.locations.espaces.upmc.fr/fr/presentation_espaces/campus_jussieu/patio.html Le Patio]<br><br>
* Enrico Di Lorenzo, [[Open_Source_Parasitic_Extraction|''Open Source parasitic extraction - solutions, challenges, and business models'']], [http://www.fastfieldsolvers.com FastFieldSolvers]
* 16:30-17:00, Pirouz Bazargan Sabet, ''[[Functional abstraction]]'', [https://www.lip6.fr/actualite/personnes-fiche.php?ident=P87 Sorbonne Université and LIP6 Laboratory]
* Tim Edwards, ''[[The Raven chip: First-time silicon success with qflow and efabless]]'', [http://opencircuitdesign.com/ Open Circuit Design, Qflow]
* 17:00-17:30, Enrico Di Lorenzo, [[Open_Source_Parasitic_Extraction|''Open Source parasitic extraction - solutions, challenges, and business models'']], [http://www.fastfieldsolvers.com FastFieldSolvers]
* Andreas Westerwick, ''[[Libre Silicon Compiler]]'', [http://libresilicon.com/ LibreSilicon]  
* 17:30-18:00, Tim Edwards, ''[[The Raven chip: First-time silicon success with qflow and efabless]]'', [http://opencircuitdesign.com/ Open Circuit Design, Qflow]
* Hagen Sankowski, ''[[Somebody is using the Advanced Library Format (ALF)? We like to do!]]'', [http://libresilicon.com/ LibreSilicon]
* 18:00-18:30, Andreas Westerwick, ''[[Libre Silicon Compiler]]'', [http://libresilicon.com/ LibreSilicon]  
* 18:30-19:00, Hagen Sankowski, ''[[Somebody is using the Advanced Library Format (ALF)? We like to do!]]'', [http://libresilicon.com/ LibreSilicon]


===High-level digital design (session II)===
====Evening program "beer & baguette" at the on-campus Tour Zamansky, 24th floor (room with a view)====
* Florent Kermarrec, ''[[LiteX: an open-source SoC builder and libraty based on Migen Python DSL]]'', [http://enjoy-digital.fr/ Enjoy Digital]
* 18:30-21:00: drinks are served
* 19:30: dinner is served
* 21:00: end of the day


=== March 16, Saturday (Day 3) ===
=== March 16, Saturday (Day 3) ===
====High-level digital design (session III)====
==== Morning Coffee ====
* Guillaume Delbergue, ''[[Toward a collaborative environment for Open Hardware Design]]'', [https://www.hiventive.com/ Hiventive]
* 8:30-9:00, Early bird coffee and tea
* Mark Burton, ''[[High level system modelling, hands-on computer session]]'', [https://www.greensocs.com/about-us GreenSocs], '''(Tutorial)'''
 
====Licenses====
* 9:00-9:30, Tristan Gingold, ''[[CERN OHL v2 draft]]'', [https://www.ohwr.org/project/cernohl/wikis/CERN-OHL-v2-draft CERN]
 
====High-level digital design (session II)====
* 9:30-10:00, Guillaume Delbergue, ''[[Toward a collaborative environment for Open Hardware Design]]'', [https://www.hiventive.com/ Hiventive]
* 10:00-11:00, Frédéric Pétrot, ''[[High level system modelling, hands-on computer session]]'', [https://www.greensocs.com/about-us GreenSocs], '''(Tutorial)'''


====Analog back-end design====
====Analog back-end design====
* Abhaya Chandra Kammara, ''[[ABSYNTH: Analog Design Automation - An approach to bring VLSI analog design to the hobbyists/non-professionals]]'', [https://www.eit.uni-kl.de/koenig/gemeinsame_seiten/projects/Research%20Projects.htm TU Kaiserslautern]
* 11:00-11:30, Marie-Minerve Louërat, ''[[From filters to CMOS transistors - A library of analog schematics with automated sizing]]'', [https://www-soc.lip6.fr/en/team-cian/ LIP6]
* Marie-Minerve Louërat, ''[[From filters to CMOS transistors - A library of analog schematics with automated sizing]]'', [https://www-soc.lip6.fr/en/team-cian/ LIP6]
* 11:30-12:00, Abhaya Chandra Kammara, ''[[ABSYNTH: Analog Design Automation - An approach to bring VLSI analog design to the hobbyists/non-professionals]]'', [https://www.eit.uni-kl.de/koenig/gemeinsame_seiten/projects/Research%20Projects.htm TU Kaiserslautern]
* 12:00-12:30, discussions<br><br>
* '''12:30-13:30''', '''lunch''' is served at the on-campus [http://www.locations.espaces.upmc.fr/fr/presentation_espaces/campus_jussieu/patio.html Le Patio]


====Back-end design====
====Back-end design====
* [https://www.lip6.fr/actualite/personnes-fiche.php?ident=P109 Jean-Paul Chaput], ''[[The Alliance/Coriolis design flow]]'', [https://www-soc.lip6.fr/equipe-cian/logiciels LIP6], '''(Tutorial)'''
* 13:30-14:30, [https://www.lip6.fr/actualite/personnes-fiche.php?ident=P109 Jean-Paul Chaput], ''[[The Alliance/Coriolis design flow]]'', [https://www-soc.lip6.fr/equipe-cian/logiciels LIP6], '''(Tutorial)'''
* Matthias Köfferlein, ''[[Hands-on with KLayout: Design rule checks and layout to netlist tools]]'', [https://klayout.de KLayout], '''(Tutorial)'''
* 14:30-15:45, Matthias Köfferlein, ''[[Hands-on with KLayout: Design rule checks and layout to netlist tools]]'', [https://klayout.de KLayout], '''(Tutorial)'''
 
* 15:45-16:00, conclusions
== Time schedule ==
===Day 1===
 
On the first day the talks begin later for allowing some people to travel in the morning.
* 9:00: registration opens
* 9:30: welcome
* 10:00: first session
* 12:30-13:30: lunch is served at the on-campus [http://www.locations.espaces.upmc.fr/fr/presentation_espaces/campus_jussieu/patio.html Le Patio]
* 18:30: end of last session
 
* 18:30-19:30: break
 
The evening program "beer & baguette" continues at the on-campus [http://www.locations.espaces.upmc.fr/fr/presentation_espaces/campus_jussieu/caves_esclangon.html ''caves Esclangon'']
* 18:30-23:00: drinks are served
* 19:30: dinner is served
* 23:00: end of the day
 
===Day 2===
* 9:00: first session
* 12:30-13:30: lunch is served at the on-campus [http://www.locations.espaces.upmc.fr/fr/presentation_espaces/campus_jussieu/patio.html Le Patio]
* 18:30: end of last session
* 18:30-19:30: break
 
The evening program "beer & baguette" continues at the on-campus [http://www.locations.espaces.upmc.fr/fr/presentation_espaces/campus_jussieu/caves_esclangon.html ''caves Esclangon'']
* 18:30-23:00: drinks are served
* 19:30: dinner is served
* 23:00: end of the day
 
===Day 3===
* 9:00: first session
* 12:30-13:30: lunch is served at the on-campus [http://www.locations.espaces.upmc.fr/fr/presentation_espaces/campus_jussieu/patio.html Le Patio]
* 16:00: end of last session


== Practical information ==
== Practical information ==

Revision as of 14:45, 18 March 2019

Free Silicon Conference 2019
Fsic2019 logo.svg
GenreFree software and free hardware development conference
Location(s)Paris, Sorbonne Université
CountryFrance
Websitewiki.f-si.org/index.php/FSiC2019

The second Free Silicon Conference (FSiC) will be held at Sorbonne Université (Paris) on March 14-16 2019. The conference will bring together experts and enthusiasts who want to build a complete Free and Open Source CAD ecosystem for designing analog and digital integrated circuits. The conference will cover the full spectrum of the design process, from system architecture, to layout and verification. The conference consists of three full days, including a Saturday for facilitating those who are involved as non-professionals. After the daily talks, the discussion will continue until late in an informal and relaxed atmosphere at the on-campus caves Esclangon.

Participation

Attending the conference is free of charge. Lunches, dinners and drinks will be offered. However, due to the limited number of spaces available, seats must be reserved before February *21* by writing at fsic2019 'at' f-si.org.

The submission window closed on January 31 2019.

Organizing committee

  • Marie-Minerve Louërat, Lip6, CNRS
  • Roselyne Chotin, Lip6, Sorbonne Université
  • Jean-Paul Chaput, Lip6, Sorbonne Université
  • Luca Alloatti, ETH-Zurich
  • Matthias Koefferlein, KLayout project
  • Sean Cross, Kosagi
  • Thomas Kramer, ETH-Zurich

Conference program

March 14, Thursday (Day 1)

Registration

  • 9:00-9:30, Registration and coffee

Welcome

Introduction and motivation for Free and Open Source (FOS) silicon

High-level digital design (session I)

Mixed-signal/analog design and transistor modelling

Evening program "beer & baguette" on-campus

  • 19:00-22:00: drinks are served
  • 19:30: dinner is served
  • 21:00: end of the day

March 15, Friday (Day 2)

Morning Coffee

  • 8:30-9:00, Early bird coffee and tea

Impact of FOS hardware

Foundries, PDKs and cell libraries

Back-end flow and algorithms

Evening program "beer & baguette" at the on-campus Tour Zamansky, 24th floor (room with a view)

  • 18:30-21:00: drinks are served
  • 19:30: dinner is served
  • 21:00: end of the day

March 16, Saturday (Day 3)

Morning Coffee

  • 8:30-9:00, Early bird coffee and tea

Licenses

High-level digital design (session II)

Analog back-end design

Back-end design

Practical information

Supporting entities

LIP6 SU CNRS logo.jpg