Difference between revisions of "FSiC2019"
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* 17:30-18:00, Felix Salfelder, ''[[GnuCap: Progress and Opportunities]]'', [https://savannah.gnu.org/git/?group=gnucap GnuCap] | * 17:30-18:00, Felix Salfelder, ''[[GnuCap: Progress and Opportunities]]'', [https://savannah.gnu.org/git/?group=gnucap GnuCap] | ||
* 18:00-18:30, [http://www.mos-ak.org/wg.html Wladek Grabinski], ''[[MOS-AK FOSS TCAD/EDA Perspective]]'', [http://mos-ak.org/ MOS-AK (EU)] | * 18:00-18:30, [http://www.mos-ak.org/wg.html Wladek Grabinski], ''[[MOS-AK FOSS TCAD/EDA Perspective]]'', [http://mos-ak.org/ MOS-AK (EU)] | ||
====Evening program "beer & baguette" at the on-campus [http://www.locations.espaces.upmc.fr/fr/presentation_espaces/campus_jussieu/caves_esclangon.html ''caves Esclangon'']==== | ====Evening program "beer & baguette" at the on-campus [http://www.locations.espaces.upmc.fr/fr/presentation_espaces/campus_jussieu/caves_esclangon.html ''caves Esclangon'']==== | ||
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==== Morning Coffee ==== | ==== Morning Coffee ==== | ||
* 8:30-9:00, Early bird coffee and tea | * 8:30-9:00, Early bird coffee and tea | ||
====Licenses==== | |||
* 9:00-9:30, Tristan Gingold, ''[[CERN OHL v2 draft]]'', [https://www.ohwr.org/project/cernohl/wikis/CERN-OHL-v2-draft CERN] | |||
====High-level digital design (session III)==== | ====High-level digital design (session III)==== | ||
* 9: | * 9:30-10:00, Guillaume Delbergue, ''[[Toward a collaborative environment for Open Hardware Design]]'', [https://www.hiventive.com/ Hiventive] | ||
* | * 10:00-11:00, Mark Burton, ''[[High level system modelling, hands-on computer session]]'', [https://www.greensocs.com/about-us GreenSocs], '''(Tutorial)''' | ||
====Analog back-end design==== | ====Analog back-end design==== | ||
* | * 11:00-11:30, Abhaya Chandra Kammara, ''[[ABSYNTH: Analog Design Automation - An approach to bring VLSI analog design to the hobbyists/non-professionals]]'', [https://www.eit.uni-kl.de/koenig/gemeinsame_seiten/projects/Research%20Projects.htm TU Kaiserslautern] | ||
* 11: | * 11:30-12:00, Marie-Minerve Louërat, ''[[From filters to CMOS transistors - A library of analog schematics with automated sizing]]'', [https://www-soc.lip6.fr/en/team-cian/ LIP6] | ||
* 12:00-12:30, discussions<br><br> | |||
* '''12:30-13:30''', '''lunch''' is served at the on-campus [http://www.locations.espaces.upmc.fr/fr/presentation_espaces/campus_jussieu/patio.html Le Patio] | |||
====Back-end design==== | ====Back-end design==== | ||
* | * 13:30-14:30, [https://www.lip6.fr/actualite/personnes-fiche.php?ident=P109 Jean-Paul Chaput], ''[[The Alliance/Coriolis design flow]]'', [https://www-soc.lip6.fr/equipe-cian/logiciels LIP6], '''(Tutorial)''' | ||
* | * 14:30-15:45, Matthias Köfferlein, ''[[Hands-on with KLayout: Design rule checks and layout to netlist tools]]'', [https://klayout.de KLayout], '''(Tutorial)''' | ||
* 15:45-16:00, conclusions | * 15:45-16:00, conclusions | ||
Revision as of 16:00, 1 March 2019
| Free Silicon Conference 2019 | |
|---|---|
 | |
| Genre | Free software and free hardware development conference |
| Location(s) | Paris, Sorbonne Université |
| Country | France |
| Website | wiki.f-si.org/index.php/FSiC2019 |
The second Free Silicon Conference (FSiC) will be held at Sorbonne Université (Paris) on March 14-16 2019. The conference will bring together experts and enthusiasts who want to build a complete Free and Open Source CAD ecosystem for designing analog and digital integrated circuits. The conference will cover the full spectrum of the design process, from system architecture, to layout and verification. The conference consists of three full days, including a Saturday for facilitating those who are involved as non-professionals. After the daily talks, the discussion will continue until late in an informal and relaxed atmosphere at the on-campus caves Esclangon.
Participation
Attending the conference is free of charge. Lunches, dinners and drinks will be offered. However, due to the limited number of spaces available, seats must be reserved before February *21* by writing at fsic2019 'at' f-si.org.
The submission window closed on January 31 2019.
Organizing committee
- Marie-Minerve Louërat, Lip6, CNRS
- Roselyne Chotin, Lip6, Sorbonne Université
- Jean-Paul Chaput, Lip6, Sorbonne Université
- Luca Alloatti, ETH-Zurich
- Matthias Koefferlein, KLayout project
- Sean Cross, Kosagi
- Thomas Kramer, ETH-Zurich
Conference program
March 14, Thursday (Day 1)
Registration
- 9:00-9:30, Registration and coffee
Welcome
- 9:35-9:45, LIP6 Director Fabrice Kordon
- 9:45-9:50, CIAN team within LIP6
- 9:50-9:55, Welcome from the Free Silicon Foundation
Introduction and motivation for Free and Open Source (FOS) silicon
- 10:00-10:30, Todd Weaver, Title to be announced, Purism
- 10:30-11:00, Steffen Reith, Towards digital sovereignty by open source (hardware), Hochschule RheinMain
High-level digital design (session I)
- 11:00-11:30, Philippe Coussy, GAUT, GAUT, Lab-STICC Université Bretagne Sud
- 11:30-12:00, Tristan Gingold, GHDL and the economy of EDA FOSS, GHDL
- 12:00-12:30, Frédéric Pétrot, High level Simulation, Université Grenoble Alpes and TIMA Laboratory
- 12:30-13:30, lunch is served at the on-campus Le Patio
- 13:30-14:00, Daniela Genius, Model-Driven Performance Evaluation and Formal Verification for Multi-level Embedded System Design , Sorbonne Université, LIP6
- 14:00-14:30, Charles Papon, From the RISC-V spec to a low-tech SoC, passing by SpinalHDL, VexRiscv and OpenOCD, SpinalHDL
- 14:30-15:00, Jean Bruant, State of the art on high-level hardware description languages to generate VHDL or SystemVerilog, OVH and TIMA Laboratory
Mixed-signal/analog design and transistor modelling
- 15:00-15:30, Christoph Grimm, SystemC AMS and upcoming free frameworks for the free design, Kaiserslautern University
- 15:30-16:00, Liliana Andrade, Mixed-signal system modelling and simulation, Université Grenoble Alpes and TIMA Laboratory
- 16:00-16:30, Afternoon break. Coffee is served at the on-campus Le Patio
- 16:30-17:00, Holger Vogt, ngspice - an open source mixed signal circuit simulator, ngspice, University Duisburg-Essen
- 17:00-17:30, Al Davis, Gnu Circuit Analysis Package (GnuCap), GnuCap
- 17:30-18:00, Felix Salfelder, GnuCap: Progress and Opportunities, GnuCap
- 18:00-18:30, Wladek Grabinski, MOS-AK FOSS TCAD/EDA Perspective, MOS-AK (EU)
Evening program "beer & baguette" at the on-campus caves Esclangon
- 19:00-22:00: drinks are served
- 19:30: dinner is served
- 22:30: end of the day
March 15, Friday (Day 2)
Morning Coffee
- 8:30-9:00, Early bird coffee and tea
Impact of FOS hardware
- 9:00-9:30, Olivier de Fresnoye, Open Source in Healthcare, an hardware approach: the echOpen project case, echopen
- 9:30-10:00, Edmund Humenberger, ASICone. Goals, timeline, participants and tools, Symbiotic EDA
Foundries, PDKs and cell libraries
- 10:00-10:30, Jean-Christophe Crébier, CMP add on services, CMP
- 10:30-11:00, Kirti Bhanushali, Development of FreePDK: An Open-Source Process Design Kit for Advanced Technology Nodes, NCSU, FreePDK
- 11:00-11:30, Thomas Benz, Converting 45nm transistor netlists to open standards, ETH Zurich
- 11:30-12:00, Hagen Sankowski, Popcorn - or how many cells your Standard Cell Library has?, LibreSilicon
- 12:00-12:30, Naohiko Shimizu, The development of the NSXLIB standard cell scalable library, Tokai University
- 12:30-13:30, lunch is served at the on-campus Le Patio
- 13:30-14:00, Matthew Guthaus, OpenRAM, OpenRAM, UCSC
- 14:00-14:30, Thomas Kramer, FOS standard cell generator from scratch, ETH Zurich
Back-end flow and algorithms
- 14:30-15:00, Gabriel Gouvine, Placement algorithms for standard cells in Coriolis, Local Solver
- 15:00-15:30, Matthias Köfferlein, KLayout's deep verification base project, KLayout
- 15:30-16:00, Pirouz Bazargan Sabet, Functional abstraction, Sorbonne Université and LIP6 Laboratory
- 16:00-16:30, Afternoon break. Coffee is served at the on-campus Le Patio
- 16:30-17:00, Enrico Di Lorenzo, Open Source parasitic extraction - solutions, challenges, and business models, FastFieldSolvers
- 17:00-17:30, Tim Edwards, The Raven chip: First-time silicon success with qflow and efabless, Open Circuit Design, Qflow
- 17:30-18:00, Andreas Westerwick, Libre Silicon Compiler, LibreSilicon
- 18:00-18:30, Hagen Sankowski, Somebody is using the Advanced Library Format (ALF)? We like to do!, LibreSilicon
High-level digital design (session II)
- 18:30-19:00, Florent Kermarrec, LiteX: an open-source SoC builder and libraty based on Migen Python DSL, Enjoy Digital
Evening program "beer & baguette" at the on-campus caves Esclangon
- 19:00-22:00: drinks are served
- 19:30: dinner is served
- 22:30: end of the day
March 16, Saturday (Day 3)
Morning Coffee
- 8:30-9:00, Early bird coffee and tea
Licenses
- 9:00-9:30, Tristan Gingold, CERN OHL v2 draft, CERN
High-level digital design (session III)
- 9:30-10:00, Guillaume Delbergue, Toward a collaborative environment for Open Hardware Design, Hiventive
- 10:00-11:00, Mark Burton, High level system modelling, hands-on computer session, GreenSocs, (Tutorial)
Analog back-end design
- 11:00-11:30, Abhaya Chandra Kammara, ABSYNTH: Analog Design Automation - An approach to bring VLSI analog design to the hobbyists/non-professionals, TU Kaiserslautern
- 11:30-12:00, Marie-Minerve Louërat, From filters to CMOS transistors - A library of analog schematics with automated sizing, LIP6
- 12:00-12:30, discussions
- 12:30-13:30, lunch is served at the on-campus Le Patio
Back-end design
- 13:30-14:30, Jean-Paul Chaput, The Alliance/Coriolis design flow, LIP6, (Tutorial)
- 14:30-15:45, Matthias Köfferlein, Hands-on with KLayout: Design rule checks and layout to netlist tools, KLayout, (Tutorial)
- 15:45-16:00, conclusions
Practical information
- Venue, map, hotels
- Trip and hotel reimbursement procedure
- Guidelines for invited speakers
- Mediawiki template for invited speakers
Supporting entities
