Difference between revisions of "FSiC2019"

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* Jean-Christophe Crébier, ''[[CMP add on services]]'', [https://mycmp.fr/ CMP]
* Jean-Christophe Crébier, ''[[CMP add on services]]'', [https://mycmp.fr/ CMP]
* Kirti Bhanushali, ''[[Development of FreePDK: An Open-Source Process Design Kit for Advanced Technology Nodes]]'', [https://www.eda.ncsu.edu/wiki/FreePDK NCSU, FreePDK]
* Kirti Bhanushali, ''[[Development of FreePDK: An Open-Source Process Design Kit for Advanced Technology Nodes]]'', [https://www.eda.ncsu.edu/wiki/FreePDK NCSU, FreePDK]
* Speaker to be announced, ''[[LibreSilicon]]'', [http://libresilicon.com/ LibreSilicon]
* Thomas Benz, ''[[Converting 45nm transistor netlists to open standards]]'', [https://www.ethz.ch ETH Zurich]
* Thomas Benz, ''[[Converting 45nm transistor netlists to open standards]]'', [https://www.ethz.ch ETH Zurich]
* Hagen Sankowski, ''[[Popcorn - or how many cells your Standard Cell Library has?]]'', [http://libresilicon.com/ LibreSilicon]
* Naohiko Shimizu, ''[[The development of the NSXLIB standard cell scalable library]]'', [http://labo.nshimizu.com/ Tokai University]
* Naohiko Shimizu, ''[[The development of the NSXLIB standard cell scalable library]]'', [http://labo.nshimizu.com/ Tokai University]
* [https://www.soe.ucsc.edu/people/mrg Matthew Guthaus], ''[[OpenRAM]]'', [https://openram.soe.ucsc.edu/ OpenRAM, UCSC]
* [https://www.soe.ucsc.edu/people/mrg Matthew Guthaus], ''[[OpenRAM]]'', [https://openram.soe.ucsc.edu/ OpenRAM, UCSC]
* Thomas Kramer, ''[[FOS standard cell generator from scratch]]'', [https://www.ethz.ch ETH Zurich]
* Thomas Kramer, ''[[FOS standard cell generator from scratch]]'', [https://www.ethz.ch ETH Zurich]
* Kay-Uwe Giering, ''[[FET ageing predictions and their coupling to Spice simulations]]'', [https://www.eas.iis.fraunhofer.de/ Fraunhofer IIS/EAS]
* Kay-Uwe Giering, ''[[FET ageing predictions and their coupling to Spice simulations]]'', [https://www.eas.iis.fraunhofer.de/ Fraunhofer IIS/EAS]
* Matthias Köfferlein, ''[[Mask layout database and (new) verification algorithms]]'', [https://klayout.de KLayout]
* Liliana Andrade, ''[[Mixed-signal system modelling and simulation]]'', [http://tima.imag.fr/sls/ Université Grenoble Alpes and TIMA Laboratory]
* Liliana Andrade, ''[[Mixed-signal system modelling and simulation]]'', [http://tima.imag.fr/sls/ Université Grenoble Alpes and TIMA Laboratory]
* Gabriel Gouvine, ''Title to be announced'', [https://www.localsolver.com/ Local Solver]
* Gabriel Gouvine, ''Title to be announced'', [https://www.localsolver.com/ Local Solver]
* Matthias Köfferlein, ''[[KLayout's deep verification base project]]'', [https://klayout.de KLayout]
* Enrico Di Lorenzo, [[Open_Source_Parasitic_Extraction|''Open Source parasitic extraction - solutions, challenges, and business models'']], [http://www.fastfieldsolvers.com FastFieldSolvers]
* Enrico Di Lorenzo, [[Open_Source_Parasitic_Extraction|''Open Source parasitic extraction - solutions, challenges, and business models'']], [http://www.fastfieldsolvers.com FastFieldSolvers]
* Tim Edwards, ''[[The Raven chip: First-time silicon success with qflow and efabless]]'', [http://opencircuitdesign.com/ Open Circuit Design, Qflow]
* Tim Edwards, ''[[The Raven chip: First-time silicon success with qflow and efabless]]'', [http://opencircuitdesign.com/ Open Circuit Design, Qflow]
* Andreas Westerwick, ''[[Libre Silicon Compiler]]'', [http://libresilicon.com/ LibreSilicon]  
* Andreas Westerwick, ''[[Libre Silicon Compiler]]'', [http://libresilicon.com/ LibreSilicon]  
* Hagen Sankowski, ''[[Somebody is using the Advanced Library Format (ALF)? We like to do!]]'', [http://libresilicon.com/ LibreSilicon]


'''Day 3'''
'''Day 3'''
Line 66: Line 67:
* Matthias Köfferlein, ''[[Hands-on with KLayout: Design rule checks and layout to netlist tools]]'', [https://klayout.de KLayout]
* Matthias Köfferlein, ''[[Hands-on with KLayout: Design rule checks and layout to netlist tools]]'', [https://klayout.de KLayout]
* Abhaya Chandra Kammara, ''[[ABSYNTH: Analog Design Automation - An approach to bring VLSI analog design to the hobbyists/non-professionals]]'', [https://www.eit.uni-kl.de/koenig/gemeinsame_seiten/projects/Research%20Projects.htm TU Kaiserslautern]
* Abhaya Chandra Kammara, ''[[ABSYNTH: Analog Design Automation - An approach to bring VLSI analog design to the hobbyists/non-professionals]]'', [https://www.eit.uni-kl.de/koenig/gemeinsame_seiten/projects/Research%20Projects.htm TU Kaiserslautern]
* Marie-Minerve Louërat, ''[[From CMOS transistors to filters - A library of analog schematics with automated sizing]]'', [https://www-soc.lip6.fr/en/team-cian/ LIP6]


== Preliminary Program ==
== Preliminary Program ==

Revision as of 09:56, 12 February 2019

Free Silicon Conference 2019
Fsic2019 logo.svg
GenreFree software and free hardware development conference
Location(s)Paris, Sorbonne Université
CountryFrance
Websitewiki.f-si.org/index.php/FSiC2019

The second Free Silicon Conference (FSiC) will be held at Sorbonne Université (Paris) on March 14-16 2019. The conference will bring together experts and enthusiasts who want to build a complete Free and Open Source CAD ecosystem for designing analog and digital integrated circuits. The conference will cover the full spectrum of the design process, from system architecture, to layout and verification. The conference consists of three full days, including a Saturday for facilitating those who are involved as non-professionals. After the daily talks, the discussion will continue until late in an informal and relaxed atmosphere at the on-campus caves Esclangon.

Abstract submission

Everybody is welcome to propose a talk by writing to fsic2019 'at' f-si.org. The submission window opened on December 12 2018 and will close on January 31 2019. Acceptance will be communicated by February 10.

Participation

Attending the conference is free of charge. Lunches, dinners and drinks will be offered. However, due to the limited number of spaces available, places must be reserved before February 15 by writing at fsic2019 'at' f-si.org.

Organizing committee

  • Marie-Minerve Louërat, Lip6, CNRS
  • Roselyne Chotin, Lip6, Sorbonne Université
  • Jean-Paul Chaput, Lip6, Sorbonne Université
  • Luca Alloatti, ETH-Zurich
  • Matthias Koefferlein, KLayout project
  • Sean Cross, Kosagi

Confirmed invited talks

The speakers below have confirmed their attendance. Speakers who gave a tentative agreement are not yet included.

Day 1

Day 2

Day 3

Preliminary Program

March 14, Thursday (Day 1)

Introduction

  • Motivations for Free and Open Source (FOS) hardware
  • Impact on society, academia, makers, industry
  • Impact on cybersecurity
  • Politics and marketing
  • Business opportunities

High-level system requirements

  • Case studies from the perspective successful Open Hardware projects

High-level digital design (architectural and pre-layout)

  • Architectural opportunities for FOS Hardware
  • High-level hardware description languages to generate VHDL or SystemVerilog
  • Formal verification
  • High-level virtual prototyping

Analog design and simulation

  • Comparison of FOS tools: Coriolis, qucs, KiCad.
  • Ngspice
  • SystemC-AMS

March 15, Friday (Day 2)

Foundries

  • FOS hardware from the foundry's perspective: legal challenges and opportunities
  • MakeLSI

Setting up the ingredients

  • Importing PDKs into FOS formats
  • Standard cell: generators and modelling
  • Parametrized analog devices and topologies
  • Parametrized Optical devices
  • Memory generators

CAD internals and algorithms - how the tools work

  • The role of databases
  • Place algorithms
  • Routing algorithms, global and detailed
  • Timing analysis
  • Power analysis
  • Formal VHDL verification

Legal issues

  • The constrains of typical NDAs
  • Hardware FOS licenses. State-of-the-art

March 16, Saturday (Day 3)

CAD tool usage - demos

  • Synthesis
  • Place and route tools
  • Timing analysis
  • Clock distribution

Post place-and-route (P&R) verification and simulators

  • Design Rule Check
  • LVS
  • Static Timing Analysis
  • Fault modelling and Automatic Test Pattern Generators (ATPG)

Workshop

Further topics and questions raised during the conference will be discussed in plenary or in individual working groups.

Time schedule

Day 1

On the first day the talks begin later for allowing some people to travel in the morning.

  • 9:00: registration opens
  • 9:30: welcome
  • 10:00: first session
  • 12:30-13:30: lunch is served at the on-campus Le Patio
  • 18:30: end of last session
  • 18:30-19:30: break

The evening program "beer & baguette" continues at the on-campus caves Esclangon

  • 18:30-23:00: drinks are served
  • 19:30: dinner is served
  • 23:00: end of the day

Day 2

  • 9:00: first session
  • 12:30-13:30: lunch is served at the on-campus Le Patio
  • 18:30: end of last session
  • 18:30-19:30: break

The evening program "beer & baguette" continues at the on-campus caves Esclangon

  • 18:30-23:00: drinks are served
  • 19:30: dinner is served
  • 23:00: end of the day

Day 3

  • 9:00: first session
  • 12:30-13:30: lunch is served at the on-campus Le Patio
  • 16:00: end of last session

Practical information