FOS standard cell generator from scratch

• Speaker(s): Thomas Kramer

3D visualization of a 'latch' standard cell.

Abstract

Flow diagram of standard cell generation flow.

This talk will give an overview of automated standard cell and library synthesis and focus on the experiences made during the ongoing development of a cell generator. The core aspects consist of:

• Place & route inside the cell
• Transistor netlist generation & transistor sizing
• Cell characterization
• Open challenges

Software

General information

• Repository: [not yet published but will come]
• Main documentation website: [not yet published, but will come]
• Wikipedia page: TBD
• Wiki page on wiki.f-si.org: TBD

Roadmap

• ✓ Place & route of single row cells
• ✓ Generate GDS
• [in progress] Generate LEF
• ✓ Timing characterization of combinatorial cells
• [in progress] Timing characterization of sequential cells
• Timing characterization of cells with tri-state output
• Timing characterization of cells with asynchronous inputs
• ✓ Generate synthesis liberty file (currently only for combinatorial cells)
• Capacitance extraction using a field solver (maybe FasterCap)