Difference between revisions of "FOS standard cell generator from scratch"
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(Add flow diagram of stdcell generation flow.) |
m (Liberty file can already be generated for combinatorial cells.) |
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* Timing characterization of cells with tri-state output | * Timing characterization of cells with tri-state output | ||
* Timing characterization of cells with asynchronous inputs | * Timing characterization of cells with asynchronous inputs | ||
* Generate synthesis liberty file | * ✓ Generate synthesis liberty file (currently only for combinatorial cells) | ||
* Capacitance extraction using a field solver (maybe [https://www.fastfieldsolvers.com/software.htm#fastercap FasterCap]) | * Capacitance extraction using a field solver (maybe [https://www.fastfieldsolvers.com/software.htm#fastercap FasterCap]) | ||
==References== | ==References== | ||
<references /> | <references /> |
Revision as of 18:49, 4 March 2019
- Speaker(s): Thomas Kramer
Abstract
This talk will give an overview of automated standard cell and library synthesis and focus on the experiences made during the ongoing development of a cell generator. The core aspects consist of:
- Place & route inside the cell
- Transistor netlist generation & transistor sizing
- Cell characterization
Software
General information
- Repository: [not yet published but will come]
- Main documentation website: [not yet published, but will come]
- Wikipedia page: TBD
- Wiki page on wiki.f-si.org: TBD
Roadmap
- ✓ Place & route of single row cells
- ✓ Generate GDS
- [in progress] Generate LEF
- ✓ Timing characterization of combinatorial cells
- [in progress] Timing characterization of sequential cells
- Timing characterization of cells with tri-state output
- Timing characterization of cells with asynchronous inputs
- ✓ Generate synthesis liberty file (currently only for combinatorial cells)
- Capacitance extraction using a field solver (maybe FasterCap)