Difference between revisions of "FOS standard cell generator from scratch"
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* ✓ Generate GDS | * ✓ Generate GDS | ||
* [in progress] Generate LEF | * [in progress] Generate LEF | ||
* [in progress] | * [in progress] Timing characterization of combinatorial cells | ||
* Timing characterization of sequential cells | |||
* Timing of sequential cells | |||
* Generate synthesis liberty file | * Generate synthesis liberty file | ||
* Capacitance extraction using a field solver (maybe FasterCap) | * Capacitance extraction using a field solver (maybe FasterCap) | ||
Revision as of 12:13, 4 February 2019
- Speaker(s): Thomas Kramer
Abstract
This talk will give an overview of automated standard cell and library synthesis and focus on the experiences made during the ongoing development of a cell generator. The core aspects consist of:
- Place & route inside the cell
- Transistor netlist generation & transistor sizing
- Cell characterization
Software
General information
- Repository: [not yet published but will come]
- Main documentation website: [not yet published, but will come]
- Wikipedia page: TBD
- Wiki page on wiki.f-si.org: TBD
Roadmap
- ✓ Place & route of single row cells
- ✓ Generate GDS
- [in progress] Generate LEF
- [in progress] Timing characterization of combinatorial cells
- Timing characterization of sequential cells
- Generate synthesis liberty file
- Capacitance extraction using a field solver (maybe FasterCap)